JN5139/001,531 NXP Semiconductors, JN5139/001,531 Datasheet - Page 26

MCU 802.15.4 32BIT 2.4G 56-QFN

JN5139/001,531

Manufacturer Part Number
JN5139/001,531
Description
MCU 802.15.4 32BIT 2.4G 56-QFN
Manufacturer
NXP Semiconductors
Datasheet

Specifications of JN5139/001,531

Frequency
2.4GHz
Modulation Or Protocol
802.15.4
Applications
General Purpose
Power - Output
*
Sensitivity
-96dBm
Voltage - Supply
2.7 V ~ 3.6 V
Current - Receiving
37mA
Current - Transmitting
37mA
Data Interface
PCB, Surface Mount
Memory Size
96kB RAM, 192kB ROM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-20°C ~ 70°C
Package / Case
56-VFQFN
Core
RISC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Symbol detection and synchronization is performed using direct sequence correlation techniques in conjunction with
searches for the Preamble and Start-of-Frame Delimiter (SFD) fields contained in the transmitted IEEE 802.15.4
Synchronization Header (SHR).
Features are provided to support network channel selection algorithms include Energy Detection (ED), Link Quality
Indication (LQI) and fully programmable Clear Channel Assessment (CCA).
The Modem provides a digital Receive Signal Strength Indication (RSSI) that facilitates the implementation of the
IEEE 802.15.4 ED function.
The LQI is defined in the IEEE 802.15.4 standard as a characterization of the strength and/or data quality of a
received packet. The Modem produces a signal quality metric based upon correlation magnitudes, which may be
used in conjunction with the ED value to formulate the LQI.
The CCA capability of the Modem supports all modes of operation defined in the IEEE 802.15.4 standard, namely
Energy above ED threshold, Carrier Sense and Carrier Sense and/or energy above ED threshold.
8.3 Baseband Processor
The baseband processor provides all time-critical functions of the IEEE802.15.4 MAC layer. Dedicated hardware
guarantees air interface timing is precise. The MAC layer hardware/software partitioning enables software to
implement the sequencing of events required by the protocol and to schedule timed events with millisecond
resolution, and the hardware to implement specific events with microsecond timing resolution. The protocol software
layer performs the higher-layer aspects of the protocol, sending management and data messages between endpoint
and coordinator nodes, using the services provided by the baseband processor.
8.3.1 Transmit
A transmission is performed by software writing the data to be transferred into the Tx/Rx Frame Buffer, together with
parameters such as the destination address and the number of retries allowed, and programming one of the protocol
timers to indicate the time at which the frame is to be sent. This time will be determined by the software tracking the
higher-layer aspects of the protocol such as superframe timing and slot boundaries. Once the packet is prepared and
protocol timer set, the supervisor block controls the transmission. When the scheduled time arrives, the supervisor
controls the sequencing of the radio and modem to perform the type of transmission required. It can perform all the
algorithms required by IEEE802.15.4 such as CSMA/CA including retries and random backoffs without processor
intervention.
When the transmission begins, the header of the frame is constructed from the parameters programmed by the
software and sent with the frame data through the serialiser to the Modem. At the same time, the radio is prepared
26
Bitstream
Bitstream
Radio
Tx
Rx
Checksum
Checksum
Append
CSMA
Verify
Protocol Timing Engine
Supervisor
CCA
Control
Status
Deserialiser
Serialiser
Backoff
Control
Figure 19: Baseband Processor
JN-DS-JN5139 1v9
Security
Codec
Codec
Inline
AES
AES
Encrypt
Decrypt
Port
Port
© NXP Laboratories UK 2010
Protocol
Timers
Frame
Buffer
Tx/Rx
Processor
Bus

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