MAX8798AETX+T Maxim Integrated Products, MAX8798AETX+T Datasheet - Page 25

• Manufacturer Part Number: MAX8798AETX+T
• Description: Display Drivers Internal-Switch Boos t Regulator with Int
• Manufacturer: Maxim Integrated Products

Specifications of MAX8798AETX+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX8798 is a slave-only device with an I
of 9Eh. The 2-wire I
SDA) is designed to attach to a 1.8V to 4V I
Connect both SCL and SDA lines to the V
through individual pullup resistors. Calculate the
required value of the pullup resistors using:
where t
table, and C
The MAX8798 uses a nonstandard I
col with mostly standard voltage and timing parame-
ters, as defined in the following subsections.
Both data and clock lines remain HIGH. Data transfers
can be initiated only when the bus is not busy (Figure 7).
Starting from an idle bus state (both SDA and SCL are
high), a HIGH to LOW transition of the SDA line while
the clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condition
from a master device on the bus.
Figure 7. I
Figure 8. I
Integrated 3-Channel Scan Driver for TFT LCDs
SDA
SCL
FREE
BUS
R
2
2
is the rise time in the Electrical Characteristics
C Bus START, STOP, and Data Change Conditions
C Slave Address and Data Byte
BUS
CONDITION
START
S
is the total capacitance on the bus.
______________________________________________________________________________________
R
2
C-bus-like serial interface (SCL and
PULLUP
VCOM Calibrator Interface
READ BYTE: R/W = 1, MAX8798 OUTPUTS D6–D0 FOLLOWED BY PROG = 0
WRITE BYTE: R/W = 2, DATA = D6–D0, PROG = 1
PROGRAM EEPROM: R/W = 0, D6–D0 = DON'T CARE, PROG = 0
Internal-Switch Boost Regulator with
S
T
A
R
T
≤
C
BUS
t
R
START Condition (S)
DATA VALID
DATA LINE
STABLE
SLAVE ADDRESS
2
C interface proto-
1001111
2
DD
C address
Bus Free
ALLOWED
CHANGE
OF DATA
2
C bus.
supply
R/W
A
C
K
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition from
the master device.
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. The
data on the line must be changed during the LOW peri-
od of the clock signal. The master generates one clock
pulse per bit of data during write operations and the
slave device outputs 1 data bit per clock pulse during
read operations. Each data transfer is initiated with a
START condition and terminated with a STOP condition.
Two bytes are transferred between the START and
STOP conditions.
After generating a START condition, the bus master
transmits the slave address consisting of the 7-bit device
code (0b1001110 or 9Eh) for the MAX8798 (Figure 8).
For a read operation the 8th bit is 1 and for write opera-
tions it is 0. The MAX8798 monitors the bus for its corre-
sponding slave address continuously. It generates an
acknowledge bit if it recognizes its slave address and it
is not busy programming the EEPROM.
D6
D5
D4
DATA BYTE
D3
D2
D1
D0
O
G
P
R
A
C
K
STOP Condition (P)
CONDITION
O
S
T
P
STOP
P
Slave Address
Data Valid
FREE
BUS
25