NCP1601ADR2G ON Semiconductor, NCP1601ADR2G Datasheet - Page 15

IC PFC CTRL CRM/TRANSITION 8SOIC

NCP1601ADR2G

Manufacturer Part Number
NCP1601ADR2G
Description
IC PFC CTRL CRM/TRANSITION 8SOIC
Manufacturer
ON Semiconductor
Datasheet

Specifications of NCP1601ADR2G

Mode
Critical Conduction (CRM), Discontinuous (Transition)
Frequency - Switching
58kHz
Current - Startup
17µA
Voltage - Supply
12.5 V ~ 18 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Start-up Supply Current
17uA
Switching Freq
405kHz
Operating Supply Voltage (min)
-3V
Operating Supply Voltage (max)
18V
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Package Type
SOIC N
Pin Count
8
Mounting
Surface Mount
Switching Frequency
405 KHz
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
NCP1601ADR2GOS
NCP1601ADR2GOS
NCP1601ADR2GOSTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NCP1601ADR2G
Manufacturer:
ON Semiconductor
Quantity:
850
Part Number:
NCP1601ADR2G
Manufacturer:
ON/安森美
Quantity:
20 000
in the oscillator pin and the oscillator frequency is to
f
Hence, the oscillator switching frequency can be
formulated in (eq.18) and represented in Figure 38.
Synchronization Mode
with level high defined to be higher than V
typical) and level low defined to be lower than V
(3.5 V typical). An internal 9 V ESD Zener diode is
connected to the Osc pin and hence the maximum
synchronization voltage is 9 V. The circuit recognizes a
synchronization frequency by the time difference between
two falling edge instants when the synchronization signal
across the 3.5 V threshold points. The actual
synchronization threshold point is a slightly higher than the
3.5 V threshold point. The minimum synchronization pulse
width is 500 ns.
synchronization threshold point to the moment of output goes
high and there is also a typical 300 ns propagation delay from
the synchronization threshold point to the moment of crossing
3.5 V. Hence, the output goes high apparently when the sync
osc(max)
Table 1. Power Factor Controller Test Data
There is an internal capacitance C
The Osc pin (Pin 5) receives an external digital signal
There is a typical 350 ns propagation delay from
700
600
500
400
300
200
100
V
in
0
130
150
180
190
210
230
250
110
0
90
(Vac)
C osc =
(405 kHz typical) when the Osc pin is opened.
Figure 38. Osc Pin Frequency Setting
36 pF ⋅ 405 kHz
f
50
osc
P
, Oscillator Frequency (kHz)
143.4
161.1
160.5
160.9
161.6
161.7
162.0
162.2
162.8
in
f osc
(W)
100
− 36 pF
osc(int)
V
out
327
373
378
382
386
387
389
391
393
(V)
150
(36 pF typical)
sync(H)
(eq.18)
sync(L)
http://onsemi.com
I
(5 V
out
200
400
400
400
400
400
400
400
400
400
(mA)
15
signal turns to 3.5 V. A timing diagram of synchronization
mode is summarized in Figure 39.
V
to operate when the supply voltage V
for NCP1601A and 10.5 V for NCP1601B. It turns off when
the supply voltage V
ESD Zener diode is connected to the V
Hence, the operating range is 9 V to 18 V.
and 14 mA low startup current make the self- - supply design
easier. The 1.5 V UVLO hysteresis option of NCP1601B
makes it more flexible to match with the second- - stage
PWM controller biasing V
Thermal Shutdown
drive and then keeps the power switch off when the junction
temperature exceeds 140C. The output stage is then
enabled once the temperature drops below typically 95C
(i.e., 45C hysteresis). The thermal shutdown is provided
to prevent possible device failures that could result from an
accidental overheating.
Output Drive
of power MOSFET. It is capable of up to - - 500 mA and
+750 mA peak drive current and has a typical rise and fall
time of 53 and 32 ns with a 1.0 nF load.
Drive Output
Sync Signal
Clock Edge
Osc Clock
CC
Figure 39. Synchronization Mode Timing Diagram in
There are two UVLO options. The device typically starts
The 4.75 V UVLO hysteresis option of the NCP1601A
An internal thermal circuitry disables the circuit gate
The output stage of the device is designed for direct drive
(DCM)
Undervoltage Lockout (UVLO)
0.998
0.997
0.996
0.993
0.990
0.986
0.980
0.973
0.959
PF
CC
THD (%)
goes below 9 V. An 18 V internal
16
4
6
6
7
6
8
8
9
DCM
CC
supply voltage.
CC
Efficiency (%)
exceeds 13.75 V
CC
91.2
92.6
94.2
95.0
95.5
95.7
96.0
96.4
96.6
pin (Pin 8).
3.5 V
5 V

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