71M6521DEIM-DB Maxim Integrated Products, 71M6521DEIM-DB Datasheet - Page 131
71M6521DEIM-DB
Manufacturer Part Number
71M6521DEIM-DB
Description
Power Management Modules & Development Tools 71M6521DE DEMO BOARD M6521DE DEMO BOARD
Manufacturer
Maxim Integrated Products
Datasheet
1.71M6521DE-DB.pdf
(138 pages)
Specifications of 71M6521DEIM-DB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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71M652X Software User’s Guide
All interrupt sources are combined in groups, as shown in Table 6-52. The priority of each group is controlled by the
bits of SFR registers IP1 and IP0.
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one
bit in the special function register IP0 and one in IP1. If requests of the same priority level are received simultaneously,
an internal polling sequence determines which request is serviced first.
The functionality and edge polarity of the external interrupts are described in Table 6-51.
Revision 1.7
6.3.5.4
T2CON.7
T2CON.6
T2CON.5
T2CON.4
T2CON.3
T2CON.2
T2CON.1
T2CON.0
Group
Bit
0
1
2
3
4
5
Interrupt Request register (T2CON)
MSB
Interrupt Priority Level Structure
IP1.5, IP0.5
Ip1.0, IP0.0
Ip1.1, IP0.1
Ip1.2, IP0.2
Ip1.3, IP0.3
Ip1.4, IP0.4
Interrupt
External
IP Bits
Symbol
0
1
2
3
I3FR
I2FR
I3FR
© Copyright 2005-2007 TERIDIAN Semiconductor Corporation
Connection
Digital I/O High Priority
Digital I/O Low Priority
Comparator
CE_BUSY
External interrupt 0
External interrupt 1
UART 0 interrupt
Timer 0 interrupt
Timer 1 interrupt
This bit controls the polarity of external interrupt 3
This bit controls the polarity of external interrupt 2
Table 6-52: The T2CON Bit Functions
I2FR
Table 6-53: Priority Level Groups
Table 6-51: The T2CON Register
-
TERIDIAN Proprietary
UART 1 interrupt
Affected Interrupts
-
-
-
-
-
Function
see DIO_Rx
see DIO_Rx
Polarity
falling
falling
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
Flag Reset
automatic
automatic
automatic
automatic
-
LSB
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