DS8005-KIT# Maxim Integrated Products, DS8005-KIT# Datasheet - Page 18

• Manufacturer Part Number: DS8005-KIT#
• Description: Power Management Modules & Development Tools DS8005 EVAL KIT DS8005 EVAL KIT
• Manufacturer: Maxim Integrated Products

Specifications of DS8005-KIT#

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Smart Card Interface
Performance can be affected by the layout of the appli-
cation. For example, an additional cross-capacitance of
1pF between card reader contacts C2 (RST_) and C3
(CLK_) or C2 (RST_) and C7 (I/O_) can cause contact
C2 to be polluted with high-frequency noise from C3 (or
C7). In this case, include a 100pF capacitor between
contacts C2 and CGND.
Application recommendations include the following:
• Ensure there is ample ground area around the device
• The device and the host microcontroller must use the
18
and the connector; place the device very near to the
connector; decouple the V
rately. These lines are best positioned under the con-
nector.
same V
PRES_, I/OIN, 5V/3V, 1_8V, CMDVCC, and OFF are
referenced to V
external clock, also reference this pin to V
______________________________________________________________________________________
DD
supply. Pins CLKDIV1, CLKDIV2, RSTIN,
Applications Information
DD
; if pin XTAL1 is to be driven by an
DD
and V
DDA
DD
lines sepa-
.
• Trace C3 (CLK) should be placed as far as possible
• The trace connecting CGND to C5 (GND) should be
• Avoid ground loops between CGND and GND.
• Decouple V
With all these layout precautions, noise should be kept to
an acceptable level and jitter on C3 (CLK_) should be
less than 100ps. Reference layouts are available on
request.
For technical support, go to
ic.com/micro.
from the other traces.
straight (the two capacitors on C1 (V
connected to this ground trace).
are the same in the application, they should be con-
nected in a star on the main trace
DDA
and V
DD
Technical Support
separately. If two supplies
https://support.maxim-
CC_
) should be