DS31406DK Maxim Integrated Products, DS31406DK Datasheet

DS31406DK

Manufacturer Part Number

DS31406DK

Description

Power Management Modules & Development Tools DS31406 DEMO KIT DS31406 DEMO KIT

Manufacturer

Maxim Integrated Products

Datasheet

1.DS31406DK.pdf (5 pages)

Specifications of DS31406DK

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Current page: 1 of 5
Download datasheet (125Kb)

The DS31406 is a flexible, high-performance timing IC

for

synthesis applications. On each of its two input clocks

and fourteen output clocks, the device can accept or

generate nearly any frequency between 2kHz and

750MHz.

The input clocks are divided down, fractionally scaled as

needed, and continuously monitored for activity and

frequency accuracy. The best input clock is selected,

manually or automatically, as the reference clock for the

rest of the device. A flexible, high-performance digital

PLL locks to the selected reference and provides

programmable bandwidth, very high resolution holdover

capability, and truly hitless switching between input

clocks. The digital PLL is followed by a clock synthesis

subsystem which has seven fully programmable digital

frequency synthesis blocks, three high-speed low-jitter

APLLs, and 14 output clocks, each with its own 32-bit

divider and phase adjustment. The APLLs provide

fractional scaling and output jitter less than 1ps RMS.

For telecom systems, the DS31406 has all required

features and functions to serve as a central timing

function or as a line card timing IC. With a suitable

oscillator the DS31406 meets the requirements of

Stratum 2, 3E, 3, 4E, and 4, G.812 Types I–IV, G.813,

and G.8262.

Frequency Conversion Applications in a Wide Variety of

Telecom Line Cards or Timing Cards with Any Mix of

+Denotes a lead(Pb)-free/RoHS-compliant package.

SPI is a trademark of Motorola, Inc.

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple

revisions of any device may be simultaneously available through various sales channels. For information about device

errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

19-5711; Rev 0; 12/10

DS31406GN+

Equipment Types

SONET/SDH, Synchronous Ethernet and/or OTN

Ports in WAN Equipment Including MSPPs, Ethernet

Switches, Routers, DSLAMs, and Base Stations

diverse

PART

frequency

-40C to +85C

TEMP RANGE

2-Input, 14-Output, Single DPLL Timing IC

Ordering Information

General Description

conversion

ABRIDGED DATA SHEET

Applications

and

PIN-PACKAGE

256 CSBGA

frequency

with Sub-ps Output Jitter



Two Input Clocks

High-Performance DPLL

Seven Digital Frequency Synthesizers

Three Output APLLs

14 Output Clocks in Seven Groups

General Features



 Produce Any 2kHz Multiple Up to 77.76MHz

 Per-DFS Clock Phase Adjust

 Output Frequencies to 750MHz

 High Resolution Fractional Scaling for FEC and

 Less than 1ps RMS Output Jitter

 Simultaneously Produce Three Low-Jitter Rates from

 Nearly Any Frequency from <1Hz to 750MHz

 Each Group Slaves to a DFS Clock, Any APLL

 Each Has a Differential Output (3 CML, 4 LVDS/

 32-Bit Frequency Divider Per Output

 Two Sync Pulse Outputs: 8kHz and 2kHz

 Suitable Line Card IC or Timing Card IC for

 Accepts and Produces Nearly Any Frequency Up

 Internal Compensation for Local Oscillator

 SPI™ Processor Interface



64B/66B (e.g., 255/237, 255/238, 66/64) or Any

Other Scaling Requirement

the Same Reference (e.g., 622.08MHz for SONET,

255/237*622.08MHz for OTU2, and 156.25MHz for

10GE)

Clock, or Any Input Clock (Divided and Scaled)

LVPECL

Stratum 2/3E/3/4E/4, SMC, SEC/EEC, or SSU

to 750MHz Including 1Hz, 2kHz, 8kHz, NxDS1,

NxE1, DS2/J2, DS3, E3, 2.5M, 25M, 125M,

156.25M, and Nx19.44M Up to 622.08M

Frequency Error

Differential or CMOS/TTL Format

Any Frequency from 2kHz to 750MHz

Fractional Scaling for 64B/66B and FEC Scaling

(e.g., 64/66, 237/255, 238/255) or Any Other

Downscaling Requirement

Continuous Input Clock Quality Monitoring

Automatic or Manual Clock Selection

Two 2/4/8kHz Frame Sync Inputs

Hitless Reference Switching on Loss of Input

Automatic or Manual Phase Build-Out

Holdover on Loss of All Inputs

Programmable Bandwidth, 0.5mHz to 400Hz

1.8V Operation with 3.3V I/O (5V Tolerant)

)

and Separate CMOS/TTL Output

Maxim Integrated Products 1

DS31406

Features

Related parts for DS31406DK

DS31406DK Summary of contents

Page 1

... Continuous Input Clock Quality Monitoring Automatic or Manual Clock Selection Two 2/4/8kHz Frame Sync Inputs Hitless Reference Switching on Loss of Input Automatic or Manual Phase Build-Out Holdover on Loss of All Inputs Programmable Bandwidth, 0.5mHz to 400Hz ) and Separate CMOS/TTL Output 1.8V Operation with 3.3V I/O (5V Tolerant) Maxim Integrated Products 1 ...

Page 2

ABRIDGED DATA SHEET Application Example DS31406 2 ...

Page 3

ABRIDGED DATA SHEET Block Diagram DS31406 SYNC1 SYNC2 Input Clock Block IC1 POS/NEG Frequency Scaler, 8 Activity Monitor, IC2 POS/NEG Freq. Monitor, Optional Inversion (per input clock) Clock status Selector JTRST JTMS JTAG JTCLK JTDI JTDO MFSYNC PLL Bypass DFS ...

Page 4

ABRIDGED DATA SHEET Detailed Features Input Clock Features  Two input clocks, differential or CMOS/TTL signal format  Input clocks can be any frequency from 2kHz up to 750MHz  Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTU-1, OTU-2, ...

Page 5

ABRIDGED DATA SHEET Output Clock Features  14 output clock signals in seven groups  Output clock groups OC1, OC2, OC3 have a very high-speed differential output (current-mode logic, and a separate CMOS/TTL output (≤ 125MHz) ≤ 750MHz)  Output ...

Related keywords

DS31406DK datasheet
DS31406DK data sheet
DS31406DK pdf datasheet
DS31406DK component
DS31406DK part
DS31406DK distributor
DS31406DK RoHS
DS31406DK datasheet download