MAX16809EVKIT+ Maxim Integrated Products, MAX16809EVKIT+ Datasheet - Page 10

• Manufacturer Part Number: MAX16809EVKIT+
• Description: Power Management Modules & Development Tools EVAL KIT FOR MAX16809
• Manufacturer: Maxim Integrated Products

Specifications of MAX16809EVKIT+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MAX16809 Evaluation Kit
The MAX16809 EV kit uses electrolytic capacitors at the
output for filtering, so the zero produced by the ESR of
the capacitors can be low enough to be within or near
the crossover frequency. This zero should be compen-
sated using an additional pole (P4) placed at the ESR
zero location. The ESR zero frequency is calculated
using the following equation:
Use the following equation to calculate the value of C35
to place the pole (P4) at the ESR zero frequency:
If ceramic capacitors are used at the output for filtering,
the frequency of zero produced by the ESR and the
capacitance will be above the crossover frequency
(0dB gain frequency) of the feedback loop and need
not be considered in the compensation design.
LED driver circuits based on the MAX16809 device use
a high-frequency switching converter to generate the
supply voltage for LED strings. Proper care must be
taken while laying out the circuit to ensure proper opera-
tion. The switching-converter part of the circuit has
nodes with very fast voltage changes, producing high-
frequency electric fields, and branches with fast current
changes, producing high-frequency magnetic fields. As
the circuit converts power, the amplitude of these fields
will be high and can easily couple to sensitive parts of
the circuit, creating undesirable effects. Follow the
guidelines below to reduce noise as much as possible:
1) Connect the bypass capacitors from REF and VCC
2) Keep the oscillator timing capacitor and resistor
10
as close as possible to the device and connect the
capacitor grounds to the analog ground plane
using vias close to the capacitor terminals. Connect
the AGND pin of the device to the analog ground
plane using a via close to the pin. Lay the analog
ground plane on the inner layer, preferably next to
the top layer. Use the analog ground plane to cover
the entire area under critical-signal components for
the power converter.
very close to the RTCT pin and make the connec-
tion as short as possible. Connect the ground of the
timing capacitor to the analog ground plane using a
via close to the capacitor terminal. Make sure that
no switching node is present near the RTCT node
and keep the area of the copper connected to the
pin small. Keep the REF connection to the timing
resistor short and away from any switching node.
______________________________________________________________________________________
F
ZESR
C
35
=
=
2π
2
π
Layout Considerations
×
×
ESR C
F
ZESR
1
1
×
×
OUT
R
7
3) Have a power ground plane for the switching-con-
4) There are two loops in the power circuit that carry
5) The gate-drive current of the MOSFET is another
6) The drain node of the MOSFET is a switching node.
7) Keep the node area and track length on the FB pin
verter power circuit under the power components
(input filter capacitor, output filter capacitor, inductor,
MOSFET, rectifier diode, and current-sense resistor).
Connect all the ground connections to the power
ground plane using vias close to the terminals.
high-frequency switching currents. One loop is
when the MOSFET is on (from the input filter capac-
itor positive terminal, through the inductor, the
MOSFET, and the current-sense resistor, to the
input capacitor negative terminal). The other loop is
when the MOSFET is off (from the input capacitor
positive terminal, through the inductor, the rectifier
diode, and the output filter capacitor, to the input
capacitor negative terminal). Analyze these two
loops and make the loop areas as small as possi-
ble. Wherever possible, have a return path on the
power ground plane for the switching currents on
the top-layer copper tracks, or through power com-
ponents. This reduces the loop area considerably
and provide a low inductance path for the switching
currents. Reducing the loop area also reduces radi-
ation during switching.
high-frequency switching current to consider. There
are two major loops: one during the MOSFET turn-on
edge and the second during the turn-off edge. The
MOSFET turn-on loop is from the VCC bypass
capacitor positive terminal, through the MOSFET dri-
ver in the device, the gate-drive resistor, the MOS-
FET gate to source (CGS and CGD), and the current-
sense resistor to the VCC bypass capacitor negative
terminal. There is no direct path for the current from
the current-sense resistor to return to the VCC
bypass capacitor through the ground plane, as the
VCC bypass capacitor is connected to the analog
ground plane and the current-sense resistor is con-
nected to the power ground plane. The best solution
is to connect the analog ground plane to the power
ground plane directly under the MOSFET gate-drive
track. This ensures that the turn-off current also has a
return path on the ground plane.
Keep this node area small to reduce radiation and
capacitive coupling to other sensitive parts of the
circuit. However, the track should be wide enough
to carry the large switching currents.
small to reduce any noise pickup.