Features:
Supported devices:
Philips Semiconductors Inc. LPC2106 16/32 bit
ARM7TDMI-S™
Development boards for ARM, AVR, MSP430 and PIC microcontrollers
MCU: 16/32 bit LPC2106 with 128K Bytes
Program Flash, 64K Bytes RAM, RTC, 2x
UARTs, I2C, SPI, 2x 32bit TIMERS, 7x
CCR, 6x PWM, WDT, 5V tolerant I/O, up
to 60MHz operation
standard JTAG connector with ARM 2x10
pin layout for programming/debugging with
ARM-JTAG
LCD 16x2 display
Five push buttons
Dallas iButton port
Frequency input
Relay with 10A/250VAC contacts
Buzzer
status LED
RS232 interface circuit with SUB D 9 pin
connector
RESET circuit
RESET button
DEBUG jumper for JTAG enable
BSL jumper for Bootloader enable
RTCK pullup resistor
14.7456
communication setup (4x PLL = 58,9824
Mhz CPU clock)
extension headers
Power plug-in jack
single
required
three on board voltage regulators 1.8V, 3.3V
and 5V
power supply filtering capacitor
PCB: FR-4, 1.5 mm (0,062"), green
soldermask, white silkscreen component
print
Four mounting holes
Dimensions: 120x38 mm (4.75x1.5")
power
Mhz
supply:
LPC2106 ARM7TDMI-S MICROCONTROLLER
crystal
LPC-MT-2106 DEVELOPMENT BOARD FOR
Copyright(c) 2004, OLIMEX Ltd., All rights reserved.
6VAC/+9VDC
allow
easy
JTAG interface:
The JTAG connector is 2x10 pin with 0,1" step
and ARM recommended JTAG layout. PIN.1 is
marked with square pad on bottom and arrow on
top.
Note: to enable JTAG interface DBG jumper
should be shorted at the time of POWER UP.
Important: when JTAG is enabled P0.18-P1.31
ports take their JTAG alternative function no
matter of PINSEL register value, so during
debugging with JTAG these ports are not
available for the user program.
JTAG signals description:
PIN.1 (VTREF) Target voltage sense. Used to
indicate the target’s operating voltage to the
debug tool.
PIN.2 (VTARGET)
used to supply power to the debug tool.
PIN.3 (nTRST) JTAG TAP reset, this signal
should be pulled up to Vcc in target board.
PIN4,6, 8, 10,12,14,16,18,20 Ground. The Gnd-
Signal-Gnd-Signal strategy implemented on the
20-way connection scheme improves noise
immunity on the target connect cable.
PIN.5 (TDI) JTAG serial data in, should be
pulled up to Vcc on target board.
PIN.7 (TMS) JTAG TAP Mode Select, should
be pulled up to Vcc on target board.
PIN.9 (TCK) JTAG clock.
PIN.11
Implemented
implementations the host ASIC may need to
synchronize external inputs (such as JTAG
inputs) with its own internal clock.
PIN.13 (TDO) JTAG serial data out.
PIN.15 (nSRST) Target system reset.
PIN.17 (DBGRQ) Asynchronous debug request.
DBGRQ allows an external signal to force the
ARM core into debug mode, should be pull
down to GND.
PIN.19 (DBGACK) Debug acknowledge signal.
The ARM core acknowledges debug-mode in
response to a DBGRQ input.
http://www.olimex.com/dev
(RTCK)
on
JTAG
certain
Target voltage. May be
re-timed
ASIC
clock.
ARM