CY7C344-20WMB Cypress Semiconductor Corp, CY7C344-20WMB Datasheet - Page 6

• Manufacturer Part Number: CY7C344-20WMB
• Description: CPLD CY7C340 Family
• Manufacturer: Cypress Semiconductor Corp

External Asynchronous Switching Characteristics
Document #: 38-03006 Rev. **
Parameter
t
t
t
t
t
t
t
t
f
f
f
f
t
Notes:
19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the registered output signal to a combinatorial
20. This parameter is measured with a positive-edge-triggered clock at the register. For negative edge triggering, the t
21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronously clocked register. This delay plus the
22. This parameter indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can
23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate.
24. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked
25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked
26. This parameter indicates the minimum time that the previous register output data is maintained on the output pin after an asynchronous register clock input
ACO1
ACO2
AS
AH
AWH
AWL
ACF
AP
MAXA1
MAXA2
MAXA3
MAXA4
AOH
output for which the registered output signal is used as an input. Assumes no expanders are used in logic of combinatorial output or the asynchronous clock
input. This parameter is tested periodically by sampling production material.
If a given input is used to clock multiple registers with both positive and negative polarity, t
asynchronous register set-up time, t
in the asynchronous clock path. This parameter is tested periodically by sampling production material.
operate. It is assumed that no expander logic is employed in the clock signal path or data path.
If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/t
assumes no expander logic is utilized. This parameter is tested periodically by sampling production material.
mode. This frequency is least of 1/(t
clocked data-path mode. Assumes no expander logic is used.
mode by a clock signal applied to an external dedicated input or an I/O pin.
to an external dedicated input or I/O pin.
Asynchronous Clock Input to Output Delay
Asynchronous Clock Input to Local Feedback to
Combinatorial Output
Dedicated Input or Feedback Set-Up Time to
Asynchronous Clock Input
Input Hold Time from Asynchronous Clock Input
Asynchronous Clock Input HIGH Time
Asynchronous Clock Input LOW Time
Asynchronous Clock to Local Feedback Input
External Asynchronous Clock Period (1/f
External Maximum Frequency in Asynchronous
Mode 1/(t
Maximum Internal Asynchronous Frequency
1/(t
Data Path Maximum Frequency in Asynchronous
Mode
Maximum Asynchronous Register Toggle
Frequency 1/(t
Output Data Stable Time from Asynchronous Clock
Input
ACF
[4, 26]
[4, 24]
+ t
ACO1
AS
) or 1/(t
AWH
+ t
AS
AWH
AWH
+ t
AS
)
, is the minimum internal period for an asynchronously clocked state machine configuration. This delay assumes no expander logic
[4, 22]
AWL
[19]
+ t
+ t
AWL
)
Description
AWL
[4, 25]
), 1/(t
)
[4, 23]
AS
+ t
AH
), or 1/t
[4]
[4, 20]
MAX4
ACO1
. It also indicates the maximum frequency at which the device may operate in the asynchronously
)
[4, 21]
[4]
Over Operating Range
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
Com’l/Ind
Mil
AWH
should be used for both t
Min. Max. Min. Max. Min. Max.
45.4
45.4
66.6
66.6
76.9
76.9
7C344-15
13
13
40
40
15
15
7
7
7
7
6
6
7
7
15
15
30
30
18
18
[7]
AWH
and t
34.4
34.4
62.5
62.5
AWH
16
16
37
37
50
50
15
15
7C344-20
9
9
9
9
7
7
9
9
AWL
and t
.
AWL
20
20
30
30
18
18
parameters must be swapped.
30.3
30.3
7C344-25
12
12
12
12
20
20
27
27
40
40
50
50
15
15
11
11
9
9
ACO1
CY7C344
. This specification
Page 6 of 15
25
25
37
37
21
21
MHz
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns