AD5410AREZ-REEL7 Analog Devices Inc, AD5410AREZ-REEL7 Datasheet - Page 5

• Manufacturer Part Number: AD5410AREZ-REEL7
• Description: 12Bit Current Source Out DAC
• Manufacturer: Analog Devices Inc

Specifications of AD5410AREZ-REEL7

• Design Resources: Simplified 12-Bit, 4 mA-to-20 mA Output Solution Using AD5410 (CN0081)
• Settling Time: 40µs
• Number Of Bits: 12
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 950mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AC PERFORMANCE CHARACTERISTICS
AV
otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
1
2
TIMING CHARACTERISTICS
AV
otherwise noted.
Table 3.
Parameter
WRITE MODE
READBACK MODE
DAISY-CHAIN MODE
1
2
3
4
Guaranteed by design and characterization; not production tested.
Digital slew rate control feature disabled and CAP1 = CAP2 = open circuit.
Guaranteed by characterization but not production tested.
All input signals are specified with t
See Figure 2, Figure 3, and Figure 4.
C
LSDO
Output Current Settling Time
AC PSRR
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
DD
DD
1
2
3
4
5
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
= capacitive load on SDO output.
= 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DV
= 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DV
1
1, 2, 3
Limit at T
33
13
13
13
40
5
5
5
40
20
5
90
40
40
13
40
5
5
40
35
35
90
40
40
13
40
5
5
40
35
R
2
= t
MIN
F
= 5 ns (10% to 90% of DV
Min
, T
MAX
Typ
10
40
−75
Max
Unit
ns min
ns min
ns min
ns min
ns min
μs min
ns min
ns min
ns min
ns min
μs max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
CC
) and timed from a voltage level of 1.2 V.
Unit
μs
μs
dB
Rev. B | Page 5 of 28
CC
CC
Description
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
LATCH high time after a write to the control register
Data setup time
Data hold time
LATCH low time
CLEAR pulse width
CLEAR activation time
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (C
LATCH rising edge to SDO tristate
SCLK cycle time
SCLK low time
SCLK high time
LATCH delay time
LATCH high time
Data setup time
Data hold time
LATCH low time
Serial output delay time (C
Test Conditions/Comments
16 mA step, to 0.1% FSR
16 mA step, to 0.1% FSR, L = 1 mH
200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage
= 2.7 V to 5.5 V, R
= 2.7 V to 5.5 V, R
LOAD
LOAD
= 300 Ω; all specifications T
= 300 Ω; all specifications T
L SDO
L SDO
= 50 pF)
= 50 pF)
4
4
AD5410/AD5420
MIN
MIN
to T
to T
MAX
MAX
, unless
, unless