AD5452YRM-REEL Analog Devices Inc, AD5452YRM-REEL Datasheet - Page 22

• Manufacturer Part Number: AD5452YRM-REEL
• Description: IC,D/A CONVERTER,SINGLE,12-BIT,CMOS,TSSOP,8PIN
• Manufacturer: Analog Devices Inc

Specifications of AD5452YRM-REEL

• Design Resources: Unipolar, Precision DC Digital-to-Analog Conversion using AD5450/1/2/3 8-14-Bit DACs (CN0052) Precision, Bipolar, Configuration for AD5450/1/2/3 8-14bit Multiplying DACs (CN0053) AC Signal Processing Using AD5450/1/2/3 Current Output DACs (CN0054) Programmable Gain Element Using AD5450/1/2/3 Current Output DAC Family (CN0055) Single Supply Low Noise LED Current Source Driver Using a Current Output DAC in the Reverse Mode (CN0139)
• Settling Time: 160ns
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 55µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD5450/AD5451/AD5452/AD5453
Table 11.
Writing
Sequence
1
2
MICROPROCESSOR INTERFACING
Microprocessor interfacing to a AD5450/AD5451/AD5452/
AD5453 DAC is through a serial bus that uses standard protocol
and is compatible with microcontrollers and DSP processors.
The communication channel is a 3-wire interface consisting
a clock signal, a data signal, and a synchro
AD5450/AD5451/AD5452/AD
the
this is cha
AD
In
The ADSP-21xx fa
AD5451/AD5452/
logic. Figure 56 is an example of an SPI interface between t
and the ADSP-2191M. SCK of the DSP drives the serial data l
SDIN. SYNC is driven from one of the port lines, in this case
SPIxSEL .
A serial interface between the DAC and DSP SPORT is shown
in Figure 57. In this example, SPORT0 is used to transfer data to
the DAC shift register. Transmission is initiated by writing a
word to the Tx register after the SPORT has been enabled. In a
write sequence, data is clocked out upon each rising edge of the
DSP’s serial clock and clocked into the DAC input shift register
upon the falling edge of its SCLK. The update of the DAC
output takes place upon the rising edge of the SYNC signal.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 56. ADSP-2191 SPI-to-AD5450/AD5451/AD5452/AD5453 Interface
terf e
SP
def
ADSP-2191*
CONTROL BITS
-21 -to-AD545
0
ac
ault eing data valid upon the fa
nge
xx
0
b
SPIxSEL
able using the control bits in the data
MOSI
1
Data Write in
Shift Register
0x3FFF
0x3200
SCK
mily of DSPs is easily interfaced to a AD5450/
1
AD5453 DAC without the need for extra glue
0
Figure 55. AD5453 Second Write, Incomplete Data Se
0/AD5451/AD5452/AD5453
0
1
INTENDED DATA FRAME
5453 require a 16-bit word, with
0
Action Expected
Load and update 0x3FFF
Load and update 0x3200
DATA BITS
0
lling edge of SCLK, but
0
nization signal. The
AD5452/AD5453*
SYNC
SDIN
SCLK
AD5450/AD5451/
0
0
-word.
0
he DAC
0
ine,
of
Rev. E | Page 22 of 32
0
Data Transf
the Device
0x3FFF
0xF200
0
quence (
CONTROL BITS
1
Communi
p
fr
and data setup-and-hold, and SCLK width. The DAC interface
expects a t
of 13 ns minimum. See the ADSP-21xx User Manual for infor-
mation on clock and frame SYNC frequencies for the SPORT
re
Table 12. SPORT Control Register Setup
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
ITFS
SLEN
ADSP-BF5xx-to-AD5450/AD5451/AD5452
Interface
T
port that enables the processor to communicate with SPI-
compatible devices. A serial interface between the BlackFin ®
processor and the AD5450/AD5451/AD5452/AD5453 DAC is
shown in Figure 58. In this configuration, data is transferred
thro
driven by the SPIxSEL pin, which is a reconfigured
programmable flag pin.
0x3 0) and Subsequent Additional Bits (0xF200)
er
*ADDITIONAL PINS OMITTED FOR CLARITY
ossible when the following specifications are compatible:
he ADSP-BF5xx family of processors has an SPI-compatible
1
ame SYNC
gister. Table 12 shows the setup for the SPORT control register.
AD
AD
AD
to
20
ugh the MOSI (master output, slave input) pin. SYNC is
SP-2101/
SP-2103/
SP-2191*
1
1
SPORT-to-AD5450/AD5451/AD5452/AD5453 Interface
Action Carried Out
Load and update 0x3FFF
Clock data to shift register upon rising edge (0xF200
cation between two devices at a given clock s
4
( SYNC falling edge to SCLK falling edge setup time)
Figure 57. ADSP-2101/ADSP-2103/ADSP-2191
0
delay and frame SYNC setup-and-hold, data delay
1
1
1
SCLK
Setting
1
00
1
1111
TFS
DT
0
1
ACTUAL DATA FRAME
0
DATA BITS
0
Description
Alternate framing
Active low frame signal
Right justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
0
0
0
0
SYNC
SDIN
SCLK
AD5452/AD5453*
AD5450/AD5451/
/AD5453
0
0
peed is
0
)