AD5724RBREZ-REEL7 Analog Devices Inc, AD5724RBREZ-REEL7 Datasheet - Page 28

• Manufacturer Part Number: AD5724RBREZ-REEL7
• Description: Quad 12Bit DAC 0.5 LSB INL + 10ppm Ref
• Manufacturer: Analog Devices Inc

Specifications of AD5724RBREZ-REEL7

• Design Resources: Software Configurable 12-Bit Quad Channel Unipolar/Bipolar Voltage Output Using AD5724R (CN0085)
• Settling Time: 10µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Analog and Digital, Dual ±
• Power Dissipation (max): 310mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5724R/AD5734R/AD5754R
CONTROL REGISTER
The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the
control function selected. The control register options are shown in Table 24 and Table 25.
Table 24. Programming the Control Register
MSB
R/ W
0
0
0
0
Table 25. Control Register Functions
Option
NOP
Clear
Load
SDO disable
CLR select
Clamp enable
TSD enable
Table 26. CLR Select Options
CLR Select Setting
0
1
Zero
0
0
0
0
REG2
0
0
0
0
No operation instruction used in readback operations.
Description
Addressing this function sets the DAC registers to the clear code and updates the outputs.
Addressing this function updates the DAC registers and, consequently, the DAC outputs.
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
See Table 26 for a description of the CLR select operation.
Set by the user to enable the current limit clamp (default). The channel does not power down on detection of
overcurrent; the current is clamped at 20 mA.
Cleared by the user to disable the current-limit clamp. The channel powers down on detection of overcurrent.
Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown
feature (default).
REG1
1
1
1
1
Unipolar Output Range
0 V
Midscale
REG0
1
1
1
1
A2
0
0
1
1
A1
0
0
0
0
A0
0
1
0
1
DB15 to DB4
Don’t care
Rev. C | Page 28 of 32
Output CLR Value
DB3
TSD enable
Bipolar Output Range
0 V
Negative full scale
Clear, data = don’t care
Load, data = don’t care
NOP, data = don’t care
DB2
Clamp enable
DB1
CLR select
LSB
DB0
SDO disable