AD7224LRZ-18 Analog Devices Inc, AD7224LRZ-18 Datasheet - Page 7

• Manufacturer Part Number: AD7224LRZ-18
• Description: 8-BIT CMOS V-OUT DAC
• Manufacturer: Analog Devices Inc

Specifications of AD7224LRZ-18

• Settling Time: 7µs
• Number Of Bits: 8
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 75mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. B
BIPOLAR OUTPUT OPERATION
The AD7224 can be configured to provide bipolar output op-
eration using one external amplifier and two resistors. Figure 6
shows a circuit used to implement offset binary coding. In this
case
Mismatch between R1 and R2 causes gain and offset errors;
therefore, these resistors must match and track over tempera-
ture. Once again, the AD7224 can be operated in single supply
or from positive/negative supplies. Table III shows the digital
code versus output voltage relationship for the circuit of Figure
6 with R1 = R2.
AGND BIAS
The AD7224 AGND pin can be biased above system GND
(AD7224 DGND) to provide an offset “zero” analog output
voltage level. Figure 7 shows a circuit configuration to achieve
this. The output voltage, V
For a given V
duce the effective V
sure specified operation. Note that V
must be referenced to DGND.
With R1 = R2
where D is a fractional representation of the digital word in
the DAC register.
V
where D is a fractional representation of the digital word in
DAC register and can vary from 0 to 255/256.
DAC Register Contents
MSB
1 1 1 1
1 0 0 0
1 0 0 0
0 1 1 1
0 0 0 0
0 0 0 0
OUT
V
RESET
(8-BIT)
DATA
REF
LDAC
DB0
DB7
Table III. Bipolar (Offset Binary) Code Table
WR
= V
CS
V
BIAS
O
IN
Figure 6. Bipolar Output Circuit
, increasing AGND above system GND will re-
1 1 1 1
0 0 0 1
0 0 0 0
1 1 1 1
0 0 0 1
0 0 0 0
+ D
1
V
V
LSB
REF
SS
DD
DAC
R2
3
•
R1
–V
V
(V
AGND
O
REF
IN
• D V
= (2 D – 1) • V
OUT
)
AD7224
which must be at least 4 V to en-
V
, is expressed as:
DD
REF
DD
DGND
Analog Output
0 V
–
–V
–V
–V
V
V
and V
R2
REF
REF
REF
REF
REF
R1
REF
V
OUT
R1
R1, R2 = 10k
127
128
128
128
127
128
128
128
• V
SS
1
1
for the AD7224
+15V
+15V
REF
R2
–V
REF
0.1%
V
OUT
–7–
MICROPROCESSOR INTERFACE
V
IN
V
Figure 8. AD7224 to 8085A/8088 Interface
Figure 9. AD7224 to 6809/6502 Interface
BIAS
Figure 11. AD7224 to 68008 Interface
Figure 10. AD7224 to Z-80 Interface
68008
E OR 2
DTACK
E OR 2
8085A
Z-80
6809
6502
V
8088
IN
A23
R/W
AGND
A15
ALE
AD7
AD0
R/W
WR
A15
A15
A1
D7
D0
WR
A0
D7
D0
D7
D0
A0
D7
D0
A8
Figure 7. AGND Bias Circuit
*LINEAR CIRCUITRY OMITTED FOR CLARITY
*LINEAR CIRCUITRY OMITTED FOR CLARITY
*LINEAR CIRCUITRY OMITTED FOR CLARITY
*LINEAR CIRCUITRY OMITTED FOR CLARITY
EN
V
LATCH
SS
EN
ADDRESS DATA BUS
ADDRESS
ADDRESS
DECODE
ADDRESS
DECODE
DECODE
ADDRESS BUS
DAC
DATA BUS
ADDRESS BUS
ADDRESS BUS
DATA BUS
ADDRESS BUS
DATA BUS
ADDRESS
V
DECODE
REF
AD7224
DGND
LDAC
WR
DB7
DB0
CS
CS
LDAC
WR
DB7
DB0
V
CS
LDAC
WR
DB7
DB0
CS
LDAC
DB7
DB0
WR
AD7224*
DD
AD7224*
AD7224*
AD7224*
AD7224
V
OUT