AD7401AYRWZ-RL Analog Devices Inc, AD7401AYRWZ-RL Datasheet - Page 5

• Manufacturer Part Number: AD7401AYRWZ-RL
• Description: Isolated 16-Bit Sigma -Delta Modula I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7401AYRWZ-RL

• Number Of Bits: 16
• Sampling Rate (per Second): 20M
• Data Interface: Serial
• Number Of Converters: 1
• Power Dissipation (max): 93.5mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7401EBZ - BOARD EVALUATION FOR AD7401
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING SPECIFICATIONS
V
Table 2.
Parameter
f
t
t
t
t
1
2
3
4
MCLKIN
1
2
3
4
Sample tested during initial release to ensure compliance.
Mark space ratio for clock input is 40/60 to 60/40 for f
V
Measured with the load circuit of
4
4
DD1
DD1
= V
= 4.5 V to 5.5 V, V
2, 3
DD2
= 5 V
1
±
5% for f
Limit at T
20
5
25
15
0.4 × t
0.4 × t
MCLKIN
DD2
MCLKIN
MCLKIN
= 3 V to 5.5 V, T
> 16 MHz to 20 MHz.
Figure 2
MIN
MCLKIN
, T
MDAT
MAX
and defined as the time required for the output to cross 0.8 V or 2.0 V.
A
Figure 2. Load Circuit for Digital Output Timing Specifications
MCLKIN
= −40°C to +125°C, unless otherwise noted.
Unit
MHz max
MHz min
ns max
ns min
ns min
ns min
≤ 16 MHz and 48/52 to 52/48 for 16 MHz < f
TO OUTPUT
PIN
t
25pF
1
Figure 3. Data Timing
Rev. B | Page 5 of 20
C
L
200µA
200µA
I
I
t
OL
OH
2
Description
Master clock input frequency
Master clock input frequency
Data access time after MCLKIN rising edge
Data hold time after MCLKIN rising edge
Master clock low time
Master clock high time
1.6V
t
3
MCLKIN
< 20 MHz.
t
4
AD7401A