AD7862ARZ-2 Analog Devices Inc, AD7862ARZ-2 Datasheet - Page 8

• Manufacturer Part Number: AD7862ARZ-2
• Description: DUAL 12-BIT PARALLEL ADC I.C.
• Manufacturer: Analog Devices Inc

Specifications of AD7862ARZ-2

• Number Of Bits: 12
• Sampling Rate (per Second): 250k
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 75mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7862
currents, as the resistor stage is followed by a high input
impedance stage of the track/hold amplifier. For the AD7862-10,
R1 = 30 k , R2 = 7.5 k , and R3 = 10 k . For the AD7862-3,
R1 = R2 = 6.5 k and R3 is open circuit.
For the AD7862-10 and AD7862-3, the designed code transi-
tions occur on successive integer LSB values (i.e., 1 LSB,
2 LSBs, 3 LSBs . . .). Output coding is twos complement
binary with 1 LSB = FS/4096. The ideal input/output transfer
function for the AD7862-10 and AD7862-3 is shown in Table I.
Analog Input
+FSR/2 – 1 LSB
+FSR/2 – 2 LSBs
+FSR/2 – 3 LSBs
GND + 1 LSB
GND
GND – 1 LSB
–FSR/2 + 3 LSBs
–FSR/2 + 2 LSBs
–FSR/2 + 1 LSB
NOTES
1
2
The analog input section for the AD7862-2 contains no biasing
resistors, and the V
and track/hold amplifier circuitry directly. The analog input
range is 0 V to +2.5 V into a high impedance stage with an
input current of less than 500 nA. This input is benign with no
dynamic charging currents. Once again, the designed code
transitions occur on successive integer LSB values. Output
coding is straight (natural) binary with 1 LSB = FS/4096 =
2.5 V/4096 = 0.61 mV. Table II shows the ideal input/output
transfer function for the AD7862-2.
Analog Input
+FSR – 1 LSB
+FSR – 2 LSB
+FSR – 3 LSB
GND + 3 LSB
GND + 2 LSB
GND + 1 LSB
NOTES
1
2
OFFSET AND FULL-SCALE ADJUSTMENT
In most digital signal processing (DSP) applications, offset and
full-scale errors have little or no effect on system performance.
Offset error can always be eliminated in the analog domain by
ac coupling. Full-scale error effect is linear and does not cause
problems as long as the input signal is within the full dynamic
range of the ADC. Invariably, some applications will require the
input signal to span the full analog input dynamic range. In such
FSR is full-scale range = 20 V (AD7862-10) and = 5 V (AD7862-3) with
1 LSB = FSR/4096 = 4.883 mV (AD7862-10) and 1.22 mV (AD7862-3) with
FSR is full-scale range and is 2.5 V for AD7862-2 with VREF = +2.5 V.
1 LSB = FSR/4096 and is 0.61 mV for AD7862-2 with VREF = +2.5 V.
Table I. Ideal Input/Output Code Table for the AD7862-10/-3
REF IN = +2.5 V.
REF IN = +2.5 V.
Table II. Ideal Input/Output Code Table for the AD7862-2
l
1
2
2
AX/BX
pin drives the input to the multiplexer
Digital Output Code Transition
011 . . . 110 to 011 . . . 111
011 . . . 101 to 011 . . . 110
011 . . . 100 to 011 . . . 101
000 . . . 000 to 000 . . . 001
111 . . . 111 to 000 . . . 000
111 . . . 110 to 111 . . . 111
100 . . . 010 to 100 . . . 011
100 . . . 001 to 100 . . . 010
100 . . . 000 to 100 . . . 001
Digital Output Code Transition
111 . . . 110 to 111 . . . 111
111 . . . 101 to 111 . . . 110
111 . . . 100 to 111 . . . 101
000 . . . 010 to 000 . . . 011
000 . . . 001 to 000 . . . 010
000 . . . 000 to 000 . . . 001
–8–
applications, offset and full-scale error will have to be adjusted
to zero.
Figure 4 shows a circuit that can be used to adjust the offset and
full-scale errors on the AD7862 (V
is shown for example purposes only). Where adjustment is
required, offset error must be adjusted before full-scale error.
This is achieved by trimming the offset of the op amp driving
the analog input of the AD7862 while the input voltage is a
1/2 LSB below analog ground. The trim procedure is as follows:
apply a voltage of –2.44 mV (–1/2 LSB) at V
and adjust the op amp offset voltage until the ADC output code
flickers between 1111 1111 1111 and 0000 0000 0000.
Gain error can be adjusted at either the first code transition
(ADC negative full scale) or the last code transition (ADC
positive full scale). The trim procedures for both cases are as
follows:
Positive Full-Scale Adjust
Apply a voltage of +9.9927 V (FS/2 – 3/2 LSBs) at V
R2 until the ADC output code flickers between 0111 1111 1110
and 0111 1111 1111.
Negative Full-Scale Adjust
Apply a voltage of –9.9976 V (–FS + 1/2 LSB) at V
R2 until the ADC output code flickers between 1000 0000 0000
and 1000 0000 0001.
An alternative scheme for adjusting full-scale error in systems
that use an external reference is to adjust the voltage at the
VREF pin until the full-scale error for any of the channels is
adjusted out. The good full-scale matching of the channels will
ensure small full-scale errors on the other channels.
TIMING AND CONTROL
Figure 5a shows the timing and control sequence required to
obtain optimum performance (Mode 1) from the AD7862. In
the sequence shown, a conversion is initiated on the falling edge
of CONVST. This places both track/holds into hold simulta-
neously, and new data from this conversion is available in the
output register of the AD7862 3.6 s later. The BUSY signal
indicates the end of conversion, and at this time the conversion
results for both inputs are available to be read. A second
conversion is then initiated. If the multiplexer select A0 is low,
the first and second read pulses after the first conversion accesses
the result from channel A (V
Figure 4. Full-Scale Adjust Circuit
INPUT
RANGE = 10V
10k
500
10k
R1
R2
R3
*ADDITIONAL PINS OMITTED FOR CLARITY
V
1
R5
10k
10k
R4
A1
and V
A1
A2
V
AGND
on the AD7862-10 version
A1
AD7862*
respectively). The third
A1
(see Figure 4)
A1
A1
and adjust
. Adjust
REV. 0