AD7890AR-4 Analog Devices Inc, AD7890AR-4 Datasheet - Page 7

• Manufacturer Part Number: AD7890AR-4
• Description: IC,Data Acquisition System,8-CHANNEL,12-BIT,SOP,24PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Type: Data Acquisition System (DAS)r

Specifications of AD7890AR-4

• Rohs Status: RoHS non-compliant
• Resolution (bits): 12 b
• Sampling Rate (per Second): 117k
• Data Interface: Serial
• Voltage Supply Source: Single Supply
• Voltage - Supply: 0 V ~ 4.10 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 2. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Mnemonic
AGND
SMODE
DGND
C
CONVST
CLK IN
SCLK
TFS
RFS
DATA OUT
DATA IN
V
MUX OUT
DD
EXT
Description
Analog Ground. Ground reference for track/hold, comparator, and DAC.
Control Input. Determines whether the part operates in its external clocking (slave) or self-clocking (master)
serial mode. With SMODE at a logic low, the part is in its self-clocking serial mode with RFS and SCLK as
outputs. This self-clocking mode is useful for connection to shift registers or to serial ports of DSP processors.
With SMODE at a logic high, the part is in its external clocking serial mode with SCLK and RFS as inputs. This
external clocking mode is useful for connection to the serial port of microcontrollers, such as the 8xC51 and
the 68HCxx, and for connection to the serial ports of DSP processors.
Digital Ground. Ground reference for digital circuitry.
External Capacitor. An external capacitor is connected to this pin to determine the length of the internal pulse
(see the Control Register section). Larger capacitances on this pin extend the pulse to allow for settling time
delays through an external antialiasing filter or signal conditioning circuitry.
Convert Start. Edge-triggered logic input. A low-to-high transition on this input puts the track/hold into hold
and initiates conversion if the internal pulse has timed out (see the Control Register section). If the internal
pulse is active when the CONVST goes high, the track/hold does not proceed to hold until the pulse times out.
If the internal pulse times out when CONVST goes high, the rising edge of CONVST drives the track/hold into
hold and initiates conversion.
Clock Input. An external TTL-compatible clock is applied to this input pin to provide the clock source for the
conversion sequence. In the self-clocking serial mode, the SCLK output is derived from this CLK IN pin.
Serial Clock Input. In the external clocking (slave) mode (see the Serial Interface section), this is an externally
applied serial clock used to load serial data to the control register and to access data from the output register.
In the self-clocking (master) mode, the internal serial clock, which is derived from the clock input (CLK IN),
appears on this pin. Once again, it is used to load serial data to the control register and to access data from the
output register.
Transmit Frame Synchronization Pulse. Active low logic input with serial data expected after the falling edge of
this signal.
Receive Frame Synchronization Pulse. In the external clocking mode, this pin is an active low logic input with
RFS provided externally as a strobe or framing pulse to access serial data from the output register. In the self-
clocking mode, it is an active low output, which is internally generated and provides a strobe or framing pulse
for serial data from the output register. For applications which require that data be transmitted and received at
the same time, RFS and TFS should be connected together.
Serial Data Output. Sixteen bits of serial data are provided with one leading zero, preceding the three address
bits of the control register and the 12 bits of conversion data. Serial data is valid on the falling edge of SCLK for
sixteen edges after RFS goes low. Output coding from the ADC is twos complement for the AD7890-10 and
straight binary for the AD7890-4 and AD7890-2.
Serial Data Input. Serial data to be loaded to the control register is provided at this input. The first five bits of
serial data are loaded to the control register on the first five falling edges of SCLK after TFS goes low. Serial data
on subsequent SCLK edges is ignored while TFS remains low.
Positive Supply Voltage, 5 V ± 5%.
Multiplexer Output. The output of the multiplexer appears at this pin. The output voltage range from this
output is 0 V to 2.5 V for the nominal analog input range to the selected channel. The output impedance of this
output is nominally 3.5 kΩ. If no external antialiasing filter is required, MUX OUT should be connected to SHA IN.
DATA OUT
CONVST
DATA IN
SMODE
CLK IN
AGND
DGND
SCLK
C
RFS
TFS
V
EXT
DD
Figure 3. Pin Configuration
10
11
12
1
2
3
4
5
6
7
8
9
Rev. C | Page 7 of 28
(Not to Scale)
AD7890
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
REF OUT/REF IN
V
V
V
V
V
V
V
V
AGND
SHA IN
MUX OUT
IN8
IN7
IN6
IN5
IN4
IN3
IN2
IN1
AD7890