AD7999YRJZ-1RL Analog Devices Inc, AD7999YRJZ-1RL Datasheet - Page 7

• Manufacturer Part Number: AD7999YRJZ-1RL
• Description: IC,Data Acquisition System,4-CHANNEL,8-BIT,TSSOP,8PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD7999YRJZ-1RL

• Design Resources: Using AD8599 as an Ultralow Distortion Driver for the AD7999 (CN0045)
• Number Of Bits: 8
• Sampling Rate (per Second): 1M
• Data Interface: I²C, Serial
• Number Of Converters: 1
• Power Dissipation (max): 4.68mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: SOT-23-8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7999
The temperature range for the Y version is −40°C to +125°C. Unless otherwise noted, V
and T
Table 4.
Parameter
DYNAMIC PERFORMANCE
DC ACCURACY
ANALOG INPUT
REFERENCE INPUT
Signal-to-Noise and
Total Harmonic
Peak Harmonic or
Intermodulation
Second-Order Terms
Third-Order Terms
Channel-to-Channel
Full-Power Bandwidth
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Offset Error Matching
Offset Temperature Drift
Gain Error
Gain Error Matching
Gain Temperature Drift
Input Voltage Range
DC Leakage Current
Input Capacitance
V
DC Leakage Current
V
Input Impedance
REF
REF
Distortion (SINAD)
Distortion (THD)
Spurious Noise (SFDR)
Distortion (IMD)
Isolation
A
Input Voltage Range
Input Capacitance
= T
1
MIN
5
5
5
3, 6
to T
MAX
5
5
5
5
.
5
3 , 4
5
5
Min
1.2
49.5
8
0
A Version
Typ
−83
−75
−90
14
1.5
±0.04
±0.05
±0.3
±0.02
4.26
±0.06
±0.03
0.59
34
4
35
5
5
35
69
Max
−65
−65
V
±1
V
±1
2
REF
DD
Min
49.5
8
0
1.2
Rev. B | Page 7 of 28
Y Version
Typ
−83
−75
−90
14
1.5
4.26
0.59
34
4
35
5
5
35
69
Max
−65
−65
±0.1
±0.1
±0.5
±0.05
±0.175
±0.06
V
±1
V
±1
REF
DD
Unit
dB
dB
dB
dB
dB
dB
MHz
MHz
Bits
LSB
LSB
LSB
LSB
ppm/°C
LSB
LSB
ppm/°C
V
μA
pF
pF
pF
pF
V
μA
pF
pF
kΩ
DD
= 2.7 V to 5.5 V, V
Test Conditions/Comments
See the
f
f
fa = 11 kHz, fb = 9 kHz for f
3.4 MHz
fa = 5.4 kHz, fb = 4.6 kHz for f
f
@ 3 dB
@ 0.1 dB
Guaranteed no missed codes to eight bits
V
Channel 0 to Channel 2—during acquisition phase
Channel 0 to Channel 2—outside acquisition phase
Channel 3—during acquisition phase
Channel 3—outside acquisition phase
Outside conversion phase
During conversion phase
IN
IN
IN
REF
= 10 kHz sine wave for f
= 1 kHz sine wave for f
= 10 kHz
= V
AD7991/AD7995/AD7999
Sample Delay and Bit Trial Delay
IN3
/V
REF
or V
REF
DD
= 2.5 V, f
SCL
SCL
up to 400 kHz
SCL
SCL
from 1.7 MHz to 3.4 MHz
from 1.7 MHz to
up to 400 kHz
SCL
= 3.4 MHz,
section,