AD8151ASTZ Analog Devices Inc, AD8151ASTZ Datasheet
AD8151ASTZ
Specifications of AD8151ASTZ
Available stocks
Related parts for AD8151ASTZ
AD8151ASTZ Summary of contents
Page 1
FEATURES Low cost 33 × 17, fully differential, nonblocking array 3.2 Gbps per port NRZ data rate Wide power supply range: +3.3 V, –3.3 V Low power 425 mA (outputs enabled (outputs disabled) LV PECL- and LV ECL-compatible ...
Page 2
AD8151 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 Maximum Power Dissipation ..................................................... 4 ESD Caution.................................................................................. 4 Pin Configuration and Function ...
Page 3
SPECIFICATIONS @ 25° 3 Table 1. Parameter DYNAMIC PERFORMANCE Max Data Rate/Channel (NRZ) Channel Jitter RMS Channel Jitter Propagation Delay Propagation Delay Match Output Rise/Fall Time INPUT ...
Page 4
AD8151 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 2. Parameter Rating Supply Voltage V − − 5 − − V ...
Page 5
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 IN20P 2 INDICATOR IN20N IN21P 5 IN21N IN22P 8 IN22N IN23P 11 IN23N IN24P ...
Page 6
AD8151 Table 3. Pin Function Descriptions Pin No. Mnemonic 10, 13, 16, 19, 22, 25, 28, 31 34, 37, 40, 42, 46, 47, 92, 93, 99, 102, 105, 108, 111, 114, 117, 120, 123, 126, ...
Page 7
Pin No. Mnemonic 64 OUT10P OUT09N 67 OUT09P OUT08N 70 OUT08P OUT07N 73 OUT07P OUT06N 76 OUT06P OUT05N 79 OUT05P ...
Page 8
AD8151 Pin No. Mnemonic 130 IN10P 131 IN10N 133 IN11P 134 IN11N 136 IN12P 137 IN12N 140 IN13P 141 IN13N 143 IN14P 144 IN14N 146 IN15P 147 IN15N 150 V EE 151 REF 152 V SS 153 D6 154 D5 ...
Page 9
TYPICAL PERFORMANCE CHARACTERISTICS 100ps/DIV Figure 5. Eye Pattern 2.5 Gbps, PRBS 23 p-p = 43ps STD DEV = 8ps 20ps/DIV Figure 6. Jitter @ 2.5 Gbps, PRBS 23 100 (CLOCK PERIOD – JITTER p- ...
Page 10
AD8151 100 PEAK-PEAK JITTER STANDARD DEVIATION 0 1.0 1.5 2.0 DATA RATE (Gbps) Figure 11. Jitter vs. Data Rate, PRBS 23 p-p = 38ps STD DEV = 7.7ps 100ps/DIV Figure 12. ...
Page 11
STD DEV = 8ps 1.4ns/DIV Figure 17. Response, 2.5 Gbps, 32-Bit Pattern 1111 1111 0000 0000 0101 0101 0011 0011 100 2.5Gbps JITTER 3.2Gbps JITTER 0.2 0.3 ...
Page 12
AD8151 100 550 570 590 610 630 650 PROPAGATION DELAY (ps) Figure 23. Variation in Channel-to-Channel Delay, All 561 Points 100 2.5Gbps 60 50 3.2Gbps 40 30 ...
Page 13
CONTROL INTERFACE TRUTH TABLES Table 4. Basic Control Functions 1 Control Pins RESET UPDATE ...
Page 14
AD8151 CONTROL INTERFACE TIMING DIAGRAMS CS INPUTS WE INPUTS A[4:0] INPUTS D[6:0] INPUTS Table 6. First Rank Write Cycle Parameter Mnemonic Description Setup Time t Chip select to write enable CSW t Address to write enable ASW t Data to ...
Page 15
CS INPUTS UPDATE INPUTS WE INPUTS ENABLING OUT[0:16][N:P] OUTPUTS DISABLING OUT[0:16][N:P] OUTPUTS Table 8. First Rank Write Cycle and Second Rank Update Cycle Parameter Mnemonic Setup Time t CSU Hold Time t CHU Output Enable Times t UOE t WOE ...
Page 16
AD8151 RESET INPUTS DISABLING OUT[0:16][N:P] OUTPUTS Table 10. Asynchronous Reset Parameter Mnemonic Disable Time t TOD Width of Reset Pulse t TW CONTROL INTERFACE PROGRAMMING EXAMPLE The following conservative pattern connects all outputs to Input 7, except Output 16, which ...
Page 17
CONTROL INTERFACE UPDATE D[0: RANK 1 RANK 2 17 ROWS OF 7-BIT LATCHES DECODERS RE A[0:4] Figure 32. Control Interface (Simplified Schematic) The AD8151 ...
Page 18
AD8151 RE Input Second Rank Read-Enable. Forcing this pin to logic low enables the output drivers on the bidirectional D pins [6:0], entering the readback mode of operation. By selecting an output address with the A pins [4:0] and forcing ...
Page 19
CIRCUIT DESCRIPTION The AD8151 is a high speed 33 × 17 differential crosspoint switch designed for data rates up to 3.2 Gbps per channel. The AD8151 supports PECL-compatible input and output levels when operated from supply (V ...
Page 20
AD8151 To ensure proper operation, all outputs (including unused output) must be pulled high using external pull-up networks to a level within the output compliance range. If outputs from multiple AD8151s are wired together, a single pull-up network can be ...
Page 21
Data Path Supplies The data path supplies have more options for their voltage levels. The choices here affect several other areas, such as power dissipation, bypassing, and common-mode levels of the inputs and outputs. The more positive voltage supply for ...
Page 22
AD8151 Thus, the power dissipation of the high output can be ignored and the output power dissipation for each output can be assumed to occur in a single static low output that sinks the full output pro- grammed current. The ...
Page 23
APPLICATIONS INPUT AND OUTPUT BUSING Although the AD8151 is a digital part, in any application that runs at high speed, analog design details have to be given very careful consideration. At high data rates, the design of the signal channels ...
Page 24
AD8151 POWER SUPPLIES The AD8151 is designed to work with standard ECL logic levels. This means that ground and V CC supply. The shells of the I/O SMA connectors are at V potential. Thus, when operating in ...
Page 25
CONFIGURATION PROGRAMMING The board is configurable by one of two methods. For ease of use, custom software is provided that controls the AD8151 programming via the parallel port of a PC. This requires a standard printer cable that has a ...
Page 26
AD8151 SOFTWARE OPERATION Click any button in the matrix to program the input to output connection. This sends the proper programming sequence out the PC parallel port. Since only one input can be programmed to a given output at one ...
Page 27
Figure 43. Component Side Rev Page AD8151 ...
Page 28
AD8151 Figure 44. Circuit Side Rev Page ...
Page 29
Figure 45. Silkscreen Top Rev Page AD8151 ...
Page 30
AD8151 Figure 46. Solder Mask Top Rev Page ...
Page 31
Figure 47. Silkscreen Bottom Rev Page AD8151 ...
Page 32
AD8151 Figure 48. Solder Mask Bottom Rev Page ...
Page 33
Figure 49. INT1 ( Rev Page AD8151 ...
Page 34
AD8151 Figure 50. INT2 ( Rev Page ...
Page 35
0.01μ 0.01μ C29 0.01μF C31 0.01μF PIN 1 IN20P 2 INDICATOR V CC IN20N IN21P 5 IN21N IN22P ...
Page 36
AD8151 R19 R40 R58 1.65kΩ 1.65kΩ 1.65kΩ IN06P IN00P P4 P28 P16 R20 R39 R57 105Ω 105Ω 105Ω P5 P17 P29 IN00N R38 IN06N R56 R21 1.65kΩ 1.65kΩ 1.65kΩ ...
Page 37
CLK CLK P2 6 74HC14 DATA 1 OUT_EN DATA 74HC14 74HC14 ...
Page 38
... AD8151 OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD8151AST 0°C to 85°C AD8151ASTZ 1 0°C to 85°C AD8151-EVAL Pb-free part. 22.20 0.75 22.00 SQ 1.60 0.60 21.80 MAX 0.45 184 1 PIN 1 ...
Page 39
NOTES Rev Page AD8151 ...
Page 40
AD8151 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02169-0-12/05(B) Rev Page ...