AD8192ACPZ-RL7 Analog Devices Inc, AD8192ACPZ-RL7 Datasheet
AD8192ACPZ-RL7
Specifications of AD8192ACPZ-RL7
Related parts for AD8192ACPZ-RL7
AD8192ACPZ-RL7 Summary of contents
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FEATURES 2 inputs, 1 output HDMI/DVI links HDMI 1.3a receive and transmit compliant ±7 kV HBM ESD on HDMI input pins 4 TMDS channels per link Supports 250 Mbps to 2.25 Gbps data rates and beyond Supports 25 MHz to ...
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AD8192 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Typical Application ........................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 5 Thermal ...
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SPECIFICATIONS T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, DVCC = 3.3 V, AMUXVCC = 5 V, VREF_AB = 5 V, VREF_COM = AVEE = 0 V, DVEE = 0 ...
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AD8192 Parameter Symbol Rise Time Fall Time Leakage HOT PLUG DETECT Output Low Voltage VREF refers to the voltage at the VREF_AB or VREF_COM pins. VREF should be at the same supply voltage as that to which ...
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ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Rating AVCC to AVEE 3.7 V DVCC to DVEE 3.7 V DVEE to AVEE ±0.3 V VTTI AVCC + 0.6 V VTTO AVCC + 0.6 V AMUXVCC 5.5 V VREF_AB 5.5 V VREF_COM 5.5 ...
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AD8192 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. THE AD8192 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE Table 6. Pin Function Descriptions Pin No. Mnemonic 1, 10, 33, 42 AVCC 2 IN_A0 3 IP_A0 4, 13, 30, 39, ...
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Pin No. Mnemonic 37 IN_B2 38 IP_B2 40 IN_B3 41 IP_B3 43 HPD_B 44 DDC_B1 45 DDC_B0 46 CEC_O/I 47 AMUXVCC 48 VREF_COM 49 DDC_COM1 50 DDC_COM0 51 VREF_AB 52 DVEE 53 CEC_I/O 54 HPD_A 55 DDC_A1 56 DDC_A0 1 ...
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AD8192 TYPICAL PERFORMANCE CHARACTERISTICS T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2 A data rate ...
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T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2 A data rate = 2.25 Gbps, TMDS ...
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AD8192 T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2 A data rate = 2.25 Gbps, ...
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T = 27°C, AVCC = 3.3 V, VTTI = 3.3 V, VTTO = 3.3 V, AVEE = 0 V, DVEE = 0 V, differential input swing = 1000 mV, pattern = PRBS 2 A data rate = 2.25 Gbps, TMDS ...
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AD8192 THEORY OF OPERATION The primary function of the AD8192 is to switch one of two (HDMI or DVI) single link sources to one output. Each HDMI/DVI link consists of four differential, high speed channels and four auxiliary single-ended, low ...
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TX_OCL bit of the transmitter settings register. The high speed outputs must be disabled if there are no output termination resistors present in the system. The output equalizer (pre-emphasis) can be manually confi- gured ...
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AD8192 AUXILIARY MULTIPLEXER The auxiliary (low speed) lines provide switching and buffering for the DDC bus and buffering for the CEC line. The DDC buffers are bidirectional and fully support arbitration, clock synchronization, and other relevant features of a standard ...
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SERIAL CONTROL INTERFACE RESET On initial power-up any point during operation, the AD8192 register set can be restored to the default values by pulling the RESET pin to low according to the specification in Table 1. During normal ...
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AD8192 I2C_SCL GENERAL CASE FIXED PART START ADDR I2C_SDA ADDR EXAMPLE I2C_SDA 1 2 READ PROCEDURE To read data from the AD8192 register set microcontroller) needs to send the appropriate control signals to the AD8192 slave ...
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CONFIGURATION REGISTERS The serial interface configuration registers can be read and written using the I 2 least significant bit of the AD8192 I C part address is set by tying the Pin I2C_ADDR to 3.3 V (I2C_ADDR = 1b) or ...
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AD8192 HIGH SPEED DEVICE MODES REGISTER HS_EN: High Speed (TMDS) Switch Enable Bit Table 10. HS_EN Description HS_EN Description 0b High speed channels off, low power/standby mode 1b High speed channel on HS_CH: High Speed (TMDS) Source Select Bit Table ...
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TRANSMITTER SETTINGS REGISTER TX_PE[x]: High Speed (TMDS) Output Pre-Emphasis Level Select Bus (For All TMDS Channels) Table 20. TX_PE[x] Description TX_PE[x] Description 00b No pre-emphasis (0 dB) 01b Low pre-emphasis (2 dB) 10b Medium pre-emphasis (4 dB) 11b High pre-emphasis ...
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AD8192 APPLICATIONS INFORMATION D2+ D2– D1+ D1– D0+ D0– CLK+ CLK– ESD PROT. 2kΩ (OPTIONAL) +5V HPD DDC_SCL DDC_SDA CEC EDID 0.01uF EEPROM D2+ D2– D1+ D1– D0+ D0– CLK+ CLK– ESD 2kΩ PROT. (OPTIONAL) +5V HPD DDC_SCL DDC_SDA CEC ...
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CABLE LENGTHS AND EQUALIZATION The AD8192 offers two levels of programmable equalization for the high speed inputs and 12 dB. The equalizer of the AD8192 supports video data rates 2.25 Gbps and can equalize more ...
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AD8192 PCB LAYOUT GUIDELINES The AD8192 switches two distinctly different types of signals, both of which are required for HDMI and DVI video. These signal groups require different treatment when laying out a PCB. The first group of signals carries ...
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Controlling the Characteristic Impedance of a TMDS Differential Pair The characteristic impedance of a differential pair depends on a number of variables including the trace width, the distance between the two traces, the height of the dielectric material between the ...
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AD8192 the amount of parasitic trace capacitance. An example of the board stackup is shown in Figure 34. 3W SILKSCREEN LAYER 1: SIGNAL (MICROSTRIP) PCB DIELECTRIC LAYER 2: GND (REFERENCE PLANE) PCB DIELECTRIC LAYER 3: PWR (REFERENCE PLANE) PCB DIELECTRIC ...
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... SLUG. ATTACHING THE SLUG TO AN AVEE PLANE REDUCES THE JUNCTION TEMPERATURE OF THE DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS. ORDERING GUIDE Model Temperature Range AD8192ACPZ 1 −40°C to +85°C 1 AD8192ACPZ-RL7 −40°C to +85°C AD8192-EVALZ RoHS Compliant Part. 8.00 BSC SQ 0.60 MAX ...
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AD8192 NOTES Rev Page ...
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NOTES Rev Page AD8192 ...
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AD8192 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, ...