AD9219-65EB Analog Devices Inc, AD9219-65EB Datasheet - Page 5

• Manufacturer Part Number: AD9219-65EB
• Description: Quad 10-bit 65 MSPS Serial LVDS ADC EB
• Manufacturer: Analog Devices Inc

Specifications of AD9219-65EB

• Number Of Adc's: 4
• Number Of Bits: 10
• Sampling Rate (per Second): 40M
• Data Interface: Serial
• Inputs Per Adc: 2 Single
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 378mW @ 1.8 V
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9219
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter
CLOCK INPUTS (CLK+, CLK−)
LOGIC INPUTS (PDWN, SCLK/DTP)
LOGIC INPUT (CSB)
LOGIC INPUT (SDIO/ODM)
LOGIC OUTPUT (SDIO/ODM)
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)
DIGITAL OUTPUTS (D + x, D − x),
1
2
3
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details of how these tests were completed.
This is specified for LVDS and LVPECL only.
This is specified for 13 SDIO pins sharing the same connection.
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
Logic 1 Voltage (I
Logic 0 Voltage (I
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
(Low Power, Reduced Signal Option)
Logic Compliance
Differential Output Voltage (V
Output Offset Voltage (V
Output Coding (Default)
1
OH
OL
= 50 μA)
= 800 μA)
OS
OS
2
3
)
)
OD
OD
)
)
Temperature
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Rev. D | Page 5 of 52
Min
250
1.2
0
1.2
0
1.2
0
247
1.125
150
1.10
CMOS/LVDS/LVPECL
Typ
1.2
20
1.5
30
0.5
70
0.5
30
2
1.79
LVDS
LVDS
Offset binary
Offset binary
AD9219-40
Max
3.6
0.3
3.6
0.3
DRVDD + 0.3
0.3
0.05
454
1.375
250
1.30
Min
250
1.2
1.2
1.2
0
247
1.125
150
1.10
CMOS/LVDS/LVPECL
Typ
1.5
0.5
0.5
2
LVDS
LVDS
1.2
20
30
70
30
1.79
Offset binary
Offset binary
AD9219-65
Max
DRVDD + 0.3
454
250
3.6
0.3
3.6
0.3
0.3
0.05
1.375
1.30
AD9219
Unit
mV p-p
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
kΩ
pF
V
V
mV
V
mV
V