AD9268BCPZ-125 Analog Devices Inc, AD9268BCPZ-125 Datasheet - Page 10

• Manufacturer Part Number: AD9268BCPZ-125
• Description: Dual 16 Bit 125 High SNR ADC
• Manufacturer: Analog Devices Inc

Specifications of AD9268BCPZ-125

• Design Resources: Powering AD9268 with ADP2114 for Increased Efficiency (CN0137)
• Number Of Bits: 16
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Number Of Converters: 2
• Power Dissipation (max): 777mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Number Of Elements: 2
• Resolution: 16Bit
• Architecture: Pipelined
• Sample Rate: 125MSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±1V
• Differential Input: Yes
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 1.8V
• Single Supply Voltage (min): 1.7V
• Single Supply Voltage (max): 1.9V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Differential Linearity Error: ±0.5LSB(Typ)
• Integral Nonlinearity Error: ±1.5LSB(Typ)
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: LFCSP EP
• Input Signal Type: Differential
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9268
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
SPI TIMING REQUIREMENTS
Timing Diagrams
t
t
t
t
t
t
t
t
t
t
t
SSYNC
HSYNC
DS
DH
CLK
S
H
HIGH
LOW
EN_SDIO
DIS_SDIO
CH A/CH B DATA
CH A/CH B DATA
DCOA/DCOB
DCOA/DCOB
CLK+
CLK–
CLK+
CLK–
VIN
VIN
Conditions
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge
Time required for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge
N – 1
N – 1
Figure 3. CMOS Interleaved Output Mode Data Output Timing
t
t
Figure 2. CMOS Default Output Mode Data Output Timing
CH
CH
t
DCO
N – 13
t
t
PD
PD
N
N
N – 12
t
t
CH A
t
A
t
A
CLK
Rev. A | Page 10 of 44
CLK
t
DCO
t
t
N – 12
SKEW
SKEW
N – 12
CH B
N + 1
N + 1
N – 11
CH A
N – 11
N – 11
CH B
N + 2
N + 2
N – 10
CH A
N – 10
N – 10
N + 3
N + 3
CH B
CH A
N – 9
N – 9
N + 4
CH B
N – 9
N + 4
CH A
N – 8
N – 8
N + 5
N + 5
Limit
0.3 ns typ
0.40 ns typ
2 ns min
2 ns min
40 ns min
2 ns min
2 ns min
10 ns min
10 ns min
10 ns min
10 ns min