AD9272BSVZRL-65 Analog Devices Inc, AD9272BSVZRL-65 Datasheet - Page 30

• Manufacturer Part Number: AD9272BSVZRL-65
• Description: 12Bit 65 MSPS Octal ADC
• Manufacturer: Analog Devices Inc
• Type: Ultrasound Receiversr

Specifications of AD9272BSVZRL-65

• Design Resources: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
• Resolution (bits): 12 b
• Sampling Rate (per Second): 65M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8V, 3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9272-65EBZ - BOARD EVAL AD9272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9272
VGA Noise
In a typical application, a VGA compresses a wide dynamic
range input signal to within the input span of an ADC. The
input-referred noise of the LNA limits the minimum resolvable
input signal, whereas the output-referred noise, which depends
primarily on the VGA, limits the maximum instantaneous
dynamic range that can be processed at any one particular gain
control voltage. This latter limit is set in accordance with the
total noise floor of the ADC.
Output-referred noise as a function of GAIN+ is shown in
Figure 14 for the short-circuit input conditions. The input
noise voltage is simply equal to the output noise divided by
the measured gain at each point in the control range.
The output-referred noise is a flat 60 nV/√Hz (postamp gain =
24 dB) over most of the gain range because it is dominated by
the fixed output-referred noise of the VGA. At the high end of
the gain control range, the noise of the LNA and of the source
prevail. The input-referred noise reaches its minimum value
near the maximum gain control voltage, where the input-
referred contribution of the VGA is miniscule.
At lower gains, the input-referred noise, and therefore, the noise
figure, increases as the gain decreases. The instantaneous
dynamic range of the system is not lost, however, because the
input capacity increases as the input-referred noise increases.
The contribution of the ADC noise floor has the same dependence.
The important relationship is the magnitude of the VGA output
noise floor relative to that of the ADC.
Gain control noise is a concern in very low noise applications.
Thermal noise in the gain control interface can modulate the
channel gain. The resultant noise is proportional to the output
signal level and is usually evident only when a large signal is
present. The gain interface includes an on-chip noise filter, which
significantly reduces this effect at frequencies above 5 MHz. Care
should be taken to minimize noise impinging at the GAIN±
inputs. An external RC filter can be used to remove V
noise. The filter bandwidth should be sufficient to accommodate
the desired control bandwidth.
Antialiasing Filter
The filter that the signal reaches prior to the ADC is used to
reject dc signals and to band limit the signal for antialiasing.
Figure 53 shows the architecture of the filter.
AD9272
GAIN+
GAIN–
Figure 52. Differential GAIN± Pins Configuration
0.01µF
0.01µF
100Ω
100Ω
±0.4DC AT
±0.4DC AT
0.8V CM
0.8V CM
AD8138
499Ω
499Ω
0.8V CM
523Ω
499Ω
AVDD2
31.3kΩ
10kΩ
50Ω
GAIN
±0.8V DC
source
Rev. C | Page 30 of 44
The antialaising filter is a combination of a single-pole high-
pass filter and a second-order low-pass filter. The high-pass
filter can be configured at a ratio of the low-pass filter cutoff.
This is selectable through the SPI.
The filter uses on-chip tuning to trim the capacitors and in turn
set the desired cutoff frequency and reduce variations. The
default −3 dB low-pass filter cutoff is 1/3 or 1/4.5 the ADC
sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1,
1.2, or 1.3 times this frequency through the SPI. The cutoff
tolerance is maintained from 8 MHz to 18 MHz.
Tuning is normally off to avoid changing the capacitor settings
during critical times. The tuning circuit is enabled and disabled
through the SPI. Initializing the tuning of the filter must be
performed after initial power-up and after reprogramming
the filter cutoff scaling or ADC sample rate. Occasional
retuning during an idle time is recommended to compensate
for temperature drift.
There is a total of eight SPI-programmable settings that allow the
user to vary the high-pass filter cutoff frequency as a function
of the low-pass cutoff frequency. Two examples are shown in
Table 10: one is for an 8 MHz low-pass cutoff frequency and the
other is for an 18 MHz low-pass cutoff frequency. In both cases,
as the ratio decreases, the amount of rejection on the low-end
frequencies increases. Therefore, making the entire AAF
frequency pass band narrow can reduce low frequency noise or
maximize dynamic range for harmonic processing.
Table 10. SPI-Selectable High-Pass Filter Cutoff Options
SPI Setting
0
1
2
3
4
5
6
7
1
Ratio = low-pass filter cutoff frequency/high-pass filter cutoff frequency.
C = 0.8pF TO 5.1pF
n = 0 TO 7
30C
30C
Ratio
20.65
11.45
7.92
6.04
4.88
4.10
3.52
3.09
Figure 53. Simplified Filter Schematic
1
10kΩ/n
Low-Pass Cutoff
= 8 MHz
387 kHz
698 kHz
1.010 MHz
1.323 MHz
1.638 MHz
1.953 MHz
2.270 MHz
2.587 MHz
4kΩ
4kΩ
High-Pass Cutoff
4C
2kΩ
2kΩ
Low-Pass Cutoff
= 18 MHz
872 kHz
1.571 MHz
2.273 MHz
2.978 MHz
3.685 MHz
4.394 MHz
5.107 MHz
5.822 MHz
4kΩ
4kΩ
C
C