AD9272BSVZRL-80 Analog Devices Inc, AD9272BSVZRL-80 Datasheet - Page 36

• Manufacturer Part Number: AD9272BSVZRL-80
• Description: 12Bit 80 MSPS Octal ADC
• Manufacturer: Analog Devices Inc
• Type: Ultrasound Receiversr

Specifications of AD9272BSVZRL-80

• Design Resources: Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
• Resolution (bits): 12 b
• Sampling Rate (per Second): 80M
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 1.8V, 3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP Exposed Pad, 100-eTQFP, 100-HTQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9272-65EBZ - BOARD EVAL AD9272
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9272
When using the serial port interface (SPI), the DCO± phase can
be adjusted in 60° increments relative to the data edge. This
enables the user to refine system timing margins if required.
The default DCO± timing, as shown in Figure 2, is 90° relative
to the output data edge.
An 8-, 10-, and 14-bit serial stream can also be initiated from
the SPI. This allows the user to implement different serial streams
and test the compatibility of the device, with lower and higher
resolution systems. When changing the resolution to an 8- or
10-bit serial stream, the data stream is shortened. When using
the 14-bit option, the data stream stuffs two 0s at the end of the
normal 14-bit serial data.
When using the SPI, all of the data outputs can also be inverted
from their nominal state. This is not to be confused with inverting
the serial stream to an LSB-first mode. In default mode, as shown
in Figure 2, the MSB is represented first in the data output serial
stream. However, this can be inverted so that the LSB is repre-
sented first in the data output serial stream (see Figure 3).
There are 12 digital output test pattern options available that
can be initiated through the SPI. This is a useful feature when
validating receiver capture and timing. Refer to Table 12 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. Note that some
patterns may not adhere to the data format select option. In
addition, user patterns can be assigned in the 0x19, 0x1A, 0x1B,
and 0x1C register addresses. All test mode options except PN
sequence short and PN sequence long can support 8- to 14-bit
word lengths in order to verify data capture to the receiver.
The PN sequence short pattern produces a pseudorandom
bit sequence that repeats itself every 2
description of the PN sequence and how it is generated can be
found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The
only difference is that the starting value is a specific value instead
of all 1s (see Table 13 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 2
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
only differences are that the starting value is a specific value
instead of all 1s, and the AD9272 inverts the bit stream with
relation to the ITU standard (see Table 13 for the initial values).
Table 13. PN Sequence
Sequence
PN Sequence Short
PN Sequence Long
Consult the Memory Map section for information on how to
change these additional digital output timing features through the
SPI.
Initial
Value
0x0DF
0x29B80A
23
First Three Output Samples
(MSB First)
0xDF9, 0x353, 0x301
0x591, 0xFD7, 0x0A3
− 1 bits or 8,388,607 bits. A
9
− 1 bits or 511 bits. A
Rev. C | Page 36 of 44
SDIO Pin
This pin is required to operate the SPI. It has an internal 30 kΩ
pull-down resistor that pulls this pin low and is only 1.8 V
tolerant. If applications require that this pin be driven from a
3.3 V logic level, insert a 1 kΩ resistor in series with this pin to
limit the current.
SCLK Pin
This pin is required to operate the SPI port interface. It has an
internal 30 kΩ pull-down resistor that pulls this pin low and is
both 1.8 V and 3.3 V tolerant.
CSB Pin
This pin is required to operate the SPI port interface. It has an
internal 70 kΩ pull-up resistor that pulls this pin high and is both
1.8 V and 3.3 V tolerant.
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
nominally equal to 10 kΩ to ground at the RBIAS pin. Using
other than the recommended 10 kΩ resistor for RBIAS degrades
the performance of the device. Therefore, it is imperative that at
least a 1% tolerance on this resistor be used to achieve consistent
performance.
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9272. This is gained up internally by a factor of 2, setting
VREF to 1 V, which results in a full-scale differential input span
of 2 V p-p for the ADC. VREF is set internally by default, but the
VREF pin can be driven externally with a 1.0 V reference to
achieve more accuracy. However, this device does not support
ADC full-scale ranges below 2 V p-p.
When applying the decoupling capacitors to the VREF pin, use
ceramic low-ESR capacitors. These capacitors should be close to
the reference pin and on the same layer of the PCB as the AD9272.
The VREF pin should have both a 0.1 μF capacitor and a 1 μF
capacitor connected in parallel to the analog ground. These
capacitor values are recommended for the ADC to properly
settle and acquire the next valid sample.
The reference settings can be selected using the SPI. The settings
allow two options: using the internal reference or using an external
reference. The internal reference option is the default setting and
has a resulting differential span of 2 V p-p.
Table 14. SPI-Selectable Reference Settings
SPI-Selected Mode
External Reference
Internal Reference (Default)
Resulting
VREF (V)
N/A
1
Resulting Differential
Span (V p-p)
2 × external reference
2