AD9381KSTZ-100 Analog Devices Inc, AD9381KSTZ-100 Datasheet - Page 7

• Manufacturer Part Number: AD9381KSTZ-100
• Description: IC,TV/VIDEO CIRCUIT,Video Interface Circuit,CMOS,QFP,100PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Pin Type
REFERENCES
POWER SUPPLY
CONTROL
HDCP
AUDIO DATA OUTPUTS
DATA ENABLE
RTERM
Table 6. Pin Function Descriptions
Mnemonic
INPUTS
FILT
PWRDN
Rx0+
Rx0−
Rx1+
Rx1−
Rx2+
Rx2−
RxC+
RxC−
Description
Digital Input Channel 0 True.
Digital Input Channel 0 Complement.
Digital Input Channel 1 True.
Digital Input Channel 1 Complement.
Digital Input Channel 2 True.
Digital Input Channel 2 Complement.
These six pins receive three pairs of transition minimized differential signaling (TMDS) pixel data (at 10× the pixel
rate) from a digital graphics transmitter.
Digital Data Clock True.
Digital Data Clock Complement.
This clock pair receives a TMDS clock at 1× pixel data rate.
External Filter Connection.
For proper operation, the audio clock generator PLL requires an external filter. Connect the filter shown in
Figure 8 to this pin. For optimal performance, minimize noise and parasitics on this node. For more information
see the PCB Layout Recommendations section .
Power-Down Control/Three-State Control.
The function of this pin is programmable via Register 0x26 [2:1].
Pin No.
57
80, 76, 72, 67,
45, 33
100, 90, 10
59, 56, 54
48, 32, 30
83
82
49
50
51
52
28
27
26
25
24
20
21
22
23
88
46
Mnemonic
FILT
V
V
PV
DV
GND
SDA
SCL
DDCSCL
DDCSDA
PU2
PU1
S/PDIF
I
I
I
I
MCLKIN
MCLKOUT
SCLK
LRCLK
DE
RTERM
2
2
2
2
D
DD
S0
S1
S2
S3
DD
DD
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Function
Connection for External Filter Components for Audio PLL
Analog Power Supply and DVI Terminators
Output Power Supply
PLL Power Supply
Digital Logic Power Supply
Ground
Serial Port Data I/O
Serial Port Data Clock
HDCP Slave Serial Port Data Clock
HDCP Slave Serial Port Data I/O
This should be pulled up to 3.3 V through a 10 kΩ resistor
This should be pulled up to 3.3 V through a 10 kΩ resistor
S/PDIF Digital Audio Output
I
I
I
I
External Reference Audio Clock In
Audio Master Clock Output
Audio Serial Clock Output
Data Output Clock for Left and Right Audio Channels
Data Enable
Sets Internal Termination Resistance
2
2
2
2
S Audio (Channel 1, Channel 2)
S Audio (Channels 3, Channel 4)
S Audio (Channels 5, Channel 6)
S Audio (Channels 7, Channel 8)
Value
PV
3.3 V
1.8 V to 3.3 V
1.8 V
1.8 V
0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
V
V
V
V
V
V
V
V
V
3.3 V CMOS
500 Ω
DD
DD
DD
DD
DD
DD
DD
DD
DD
AD9381
DD