AD9516-1BCPZ Analog Devices Inc, AD9516-1BCPZ Datasheet - Page 4
![IC,Fourteen Distributed-Output Clock Driver,LLCC,64PIN,PLASTIC](/photos/6/50/65021/505-64-lfcsp_sml.jpg)
AD9516-1BCPZ
Manufacturer Part Number
AD9516-1BCPZ
Description
IC,Fourteen Distributed-Output Clock Driver,LLCC,64PIN,PLASTIC
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9516-1BCPZ-REEL7.pdf
(80 pages)
Specifications of AD9516-1BCPZ
Pll
Yes
Input
Clock
Output
CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
1:14
Differential - Input:output
Yes/Yes
Frequency - Max
2.65GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
2.65GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9516-1/PCBZ - BOARD EVALUATION FOR AD9516-1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9516-1BCPZ
Manufacturer:
ADI
Quantity:
591
Part Number:
AD9516-1BCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9516-1
SPECIFICATIONS
Typical is given for V
Minimum and maximum values are given over full V
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
V
V
V
RSET Pin Resistor
CPRSET Pin Resistor
BYPASS Pin Capacitor
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON-CHIP)
REFERENCE INPUTS
PHASE/FREQUENCY DETECTOR (PFD)
S
S_LVPECL
CP
PFD Input Frequency
Antibacklash Pulse Width
Frequency Range
VCO Gain (K
Tuning Voltage (V
Frequency Pushing (Open-Loop)
Phase Noise at 100 kHz Offset
Phase Noise at 1 MHz Offset
Differential Mode (REFIN, REFIN)
Dual Single-Ended Mode (REF1, REF2)
Input Capacitance
Input Frequency
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Input Frequency (AC-Coupled)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled)
Input Logic High
Input Logic Low
Input Current
VCO
)
T
)
S
= V
S_LVPECL
= 3.3 V ± 5%; V
Min
2300
0.5
0
1.35
1.30
4.0
4.4
20
0
2.0
−100
Min
3.135
2.375
V
2.7
S
S
Typ
50
1
−105
−124
250
1.60
1.50
5.3
2
2.9
6.0
Typ
3.3
4.12
5.1
220
4.8
0.8
1.3
≤ V
S
and T
CP
≤ 5.25 V; T
A
Max
3.465
V
5.25
10
Max
2650
V
0.5
250
1.75
1.60
5.9
6.4
250
250
0.8
+100
100
45
(−40°C to +85°C) variation.
S
CP
Rev. A | Page 4 of 80
−
A
Unit
nF
Unit
MHz
MHz/V
V
MHz/V
dBc/Hz
dBc/Hz
MHz
mV p-p
V
V
kΩ
kΩ
MHz
MHz
V
V
μA
pF
MHz
MHz
ns
ns
ns
V
V
V
kΩ
kΩ
V p-p
= 25°C; R
Test Conditions/Comments
3.3 V ± 5%
Nominally 2.5 V to 3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);
actual current can be calculated by: CP_lsb = 3.06/CPRSET;
connect to ground
Bypass for internal LDO regulator; necessary for LDO stability;
connect to ground
Test Conditions/Comments
See Figure 15
See Figure 10
V
spurs may increase due to CP up/down mismatch
f = 2475 MHz
f = 2475 MHz
Differential mode (can accommodate single-ended input by ac
grounding undriven input)
Frequencies below about 1 MHz should be dc-coupled;
be careful to match V
PLL figure of merit (FOM) increases with increasing slew rate;
see Figure 14
Self-bias voltage of REFIN
Self-bias voltage of REFIN
Self-biased
Self-biased
Two single-ended CMOS-compatible inputs
Slew rate > 50 V/μs
Slew rate > 50 V/μs; CMOS levels
Should not exceed V
Each pin, REFIN/REFIN (REF1/REF2)
Antibacklash pulse width = 1.3 ns, 2.9 ns
Antibacklash pulse width = 6.0 ns
Register 0x017[1:0] = 01b
Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b
Register 0x017[1:0] = 10b
SET
CP
≤ V
= 4.12 kΩ; CP
S
when using internal VCO; outside of this range, the CP
1
1
RSET
CM
S
p-p
(self-bias voltage)
= 5.1 kΩ, unless otherwise noted.
1
1