AD9516-5/PCBZ Analog Devices Inc, AD9516-5/PCBZ Datasheet - Page 44

• Manufacturer Part Number: AD9516-5/PCBZ
• Description: Clock IC With 2.5GHz On-chip VCO EB
• Manufacturer: Analog Devices Inc

Specifications of AD9516-5/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9516-5
• Primary Attributes: 2 Inputs, 14 Outputs
• Secondary Attributes: CMOS, LVDS, LVPECL Output Logic, ADIsimCLK™ Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9516-5
When the AD9516 is in a PD power-down, the chip is in the
following state:
•
•
•
•
•
•
If the AD9516 clock outputs must be synchronized to each
other, a SYNC is required upon exiting power-down (see the
Synchronizing the Outputs—SYNC Function section).
PLL Power-Down
The PLL section of the AD9516 can be selectively powered
down. There are three PLL operating modes set by 0x010[1:0],
as shown in Table 49.
In asynchronous power-down mode, the device powers down as
soon as the registers are updated.
In synchronous power-down mode, the PLL power-down is
gated by the charge pump to prevent unwanted frequency jumps.
The device goes into power-down on the occurrence of the next
charge pump event after the registers are updated.
The PLL is off (asynchronous power-down).
The CLK input buffer is off.
All dividers are off.
All LVDS/CMOS outputs are off.
All LVPECL outputs are in safe off mode.
The serial port is active and responds to commands.
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Distribution Power-Down
The distribution section can be powered down by writing
0x230[1] = 1b. This turns off the bias to the distribution section.
If the LVPECL power-down mode is normal operation (00b), it
is possible for a low impedance load on that LVPECL output to
draw significant current during this power-down. If the LVPECL
power-down mode is set to 11b, the LVPECL output is not
protected from reverse bias and can be damaged under certain
termination conditions.
Individual Clock Output Power-Down
Any of the clock distribution outputs can be powered down
individually by writing to the appropriate registers. The register
map details the individual power-down settings for each output.
The LVDS/CMOS outputs can be powered down, regardless of
their output load configuration.
The LVPECL outputs have multiple power-down modes
(see Table 53) that give some flexibility in dealing with the
various output termination conditions. When the mode is set to
10b, the LVPECL output is protected from reverse bias to
2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is
not protected from reverse bias and can be damaged under
certain termination conditions. This setting also affects the
operation when the distribution block is powered down with
0x230[1] = 1b (see the Distribution Power-Down section).
Individual Circuit Block Power-Down
Other AD9516 circuit blocks (such as CLK, REF1, and REF2)
can be powered down individually. This gives flexibility in
configuring the part for power savings whenever certain chip
functions are not needed.