AD9517-0/PCBZ Analog Devices Inc, AD9517-0/PCBZ Datasheet - Page 10

• Manufacturer Part Number: AD9517-0/PCBZ
• Description: 12-Output Clock Generator With 2.8GHz VC
• Manufacturer: Analog Devices Inc

Specifications of AD9517-0/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9517-0
• Primary Attributes: 2 Inputs, 12 Outputs, 2.8GHz VCO
• Secondary Attributes: CMOS, LVPECL & LVDS Compatible
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9517-0
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
VCO = 2.95 GHz; LVPECL = 491.52 MHz; PLL LBW = 75 kHz
VCO = 2.95 GHz; LVPECL = 122.88 MHz; PLL LBW = 75 kHz
VCO = 2.70 GHz; LVPECL = 122.88 MHz; PLL LBW = 187 kHz
VCO = 2.70 GHz; LVPECL = 61.44 MHz; PLL LBW = 187 kHz
VCO = 2.58 GHz; LVPECL = 61.44 MHz; PLL LBW = 75 kHz
VCO = 2.80 GHz; LVPECL = 155.52 MHz; PLL LBW = 12.8 kHz
VCO = 2.95 GHz; LVPECL = 77.76 MHz; PLL LBW = 12.8 kHz
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
Rev. B | Page 10 of 80
Min
Min
Min
Typ
148
342
212
320
184
304
221
345
210
334
513
544
54
79
124
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Typ
77
109
114
163
176
259
Max
Max
Max
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Test Conditions/Comments
Application example based on a typical
setup where the reference source is clean,
so a wider PLL loop bandwidth is used;
reference = 15.36 MHz; R = 1
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Application example based on a typical
setup where the reference source is jittery,
so a narrower PLL loop bandwidth is used;
reference = 19.44 MHz; R = 1
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Application example based on a typical
setup using an external 245.76 MHz VCXO
(Toyocom TCO-2112); reference = 15.36 MHz;
R = 1
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz