AD9517-1ABCPZ Analog Devices Inc, AD9517-1ABCPZ Datasheet - Page 10
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AD9517-1ABCPZ
Manufacturer Part Number
AD9517-1ABCPZ
Description
12-Output Clock Generator With 2.5GHz VC
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9517-1ABCPZ-RL7.pdf
(80 pages)
Specifications of AD9517-1ABCPZ
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVDS, LVPECL
Number Of Circuits
1
Ratio - Input:output
1:12
Differential - Input:output
Yes/Yes
Frequency - Max
2.65GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LFCSP
Frequency-max
2.65GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9517-1
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
VCO = 2.46 GHz; LVPECL = 491.52 MHz; PLL LBW = 55 kHz
VCO = 2.46 GHz; LVPECL = 122.88 MHz; PLL LBW = 55 kHz
VCO = 2.46 GHz; LVPECL = 61.44 MHz; PLL LBW = 55 kHz
VCO = 2.49 GHz; LVPECL = 622.08 MHz; PLL LBW = 125 Hz
VCO = 2.49 GHz; LVPECL = 155.52 MHz; PLL LBW = 125 Hz
VCO = 2.46 GHz; LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
Min
Min
Min
Rev. B | Page 10 of 80
Typ
142
370
145
356
195
402
Typ
745
712
700
Typ
54
77
109
79
114
163
124
176
259
Max
Max
Max
Unit
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Unit
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Unit
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Test Conditions/Comments
Application example based on a typical setup
where the reference source is clean, so a wider PLL
loop bandwidth is used; reference = 15.36 MHz;
R = 1
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Application example based on a typical
setup where the reference source is jittery,
so a narrower PLL loop bandwidth is used;
reference = 10.0 MHz; R = 20
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Application example based on a typical
setup using an external 245.76 MHz VCXO
(Toyocom TCO-2112); reference = 15.36 MHz;
R = 1
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz