AD9517-4ABCPZ Analog Devices Inc, AD9517-4ABCPZ Datasheet - Page 12

• Manufacturer Part Number: AD9517-4ABCPZ
• Description: 12OutputClock Generator With 1.8 GHz VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9517-4ABCPZ

• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:12
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.8GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9517-4
DELAY BLOCK ADDITIVE TIME JITTER
Table 13.
Parameter
DELAY BLOCK ADDITIVE TIME JITTER
1
SERIAL CONTROL PORT
Table 14.
Parameter
CS (INPUT)
SCLK (INPUT)
SDIO (WHEN INPUT)
SDIO, SDO (OUTPUTS)
TIMING
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of squares (RSS) method.
100 MHz Output
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Output Logic 1 Voltage
Output Logic 0 Voltage
Clock Rate (SCLK, 1/t
Pulse Width High, t
Pulse Width Low, t
SDIO to SCLK Setup, t
SCLK to SDIO Hold, t
SCLK to Valid SDIO and SDO, t
CS to SCLK Setup and Hold, t
CS Minimum Pulse Width High, t
Delay (1600 μA, 1C) Fine Adj. 000000
Delay (1600 μA, 1C) Fine Adj. 101111
Delay (800 μA, 1C) Fine Adj. 000000
Delay (800 μA, 1C) Fine Adj. 101111
Delay (800 μA, 4C) Fine Adj. 000000
Delay (800 μA, 4C) Fine Adj. 101111
Delay (400 μA, 4C) Fine Adj. 000000
Delay (400 μA, 4C) Fine Adj. 101111
Delay (200 μA, 1C) Fine Adj. 000000
Delay (200 μA, 1C) Fine Adj. 101111
Delay (200 μA, 4C) Fine Adj. 000000
Delay (200 μA, 4C) Fine Adj. 101111
LOW
HIGH
DH
SCLK
DS
)
S
, t
DV
H
PWH
1
Min
Min
2.0
2.0
2.0
2.7
16
16
2
1.1
2
3
Typ
0.54
0.60
0.65
0.85
0.79
1.2
1.2
2.0
1.3
2.5
1.9
3.8
Typ
110
2
110
2
10
20
2
Rev. B | Page 12 of 80
Max
Max
0.8
3
0.8
1
0.8
0.4
25
8
Unit
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
Unit
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
nA
nA
pF
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
Incremental additive jitter
Test Conditions/Comments
CS has an internal 30 kΩ pull-up resistor
SCLK has an internal 30 kΩ pull-down resistor