AD9518-0BCPZ-REEL7 Analog Devices Inc, AD9518-0BCPZ-REEL7 Datasheet - Page 57
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AD9518-0BCPZ-REEL7
Manufacturer Part Number
AD9518-0BCPZ-REEL7
Description
IC,Six Distributed-Output Clock Driver,LLCC,48PIN,PLASTIC
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9518-0ABCPZ-RL7.pdf
(64 pages)
Specifications of AD9518-0BCPZ-REEL7
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
LVPECL
Number Of Circuits
1
Ratio - Input:output
1:6
Differential - Input:output
Yes/Yes
Frequency - Max
2.95GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-LFCSP
Frequency-max
2.95GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9518-0/PCBZ - BOARD EVAL FOR AD9518-0
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 46. LVPECL Channel Dividers
Reg.
Addr.
(Hex)
0x190
0x191
0x192
0x193
0x194
0x195
Bits
[7:4]
[3:0]
7
6
5
4
[3:0]
1
0
[7:4]
[3:0]
7
6
5
4
[3:0]
1
0
Name
Divider 0 low cycles
Divider 0 high cycles
Divider 0 bypass
Divider 0 nosync
Divider 0 force high
Divider 0 start high
Divider 0 phase offset
Divider 0 direct to output
Divider 0 DCCOFF
Divider 1 low cycles
Divider 1 high cycles
Divider 1 bypass
Divider 1 nosync
Divider 1 force high
Divider 1 start high
Divider 1 phase offset
Divider 1 direct to output
Divider 1 DCCOFF
Description
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypasses and powers down the divider; routes input to divider output.
0: uses divider.
1: bypasses divider (default).
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default = 0x0).
Connects OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.
0: OUT0 and OUT1 are connected to Divider 0 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0xB).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0xB).
Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default = 0x0).
Connects OUT2 and OUT3 to Divider 1 or directly to VCO or CLK.
0: OUT2 and OUT3 are connected to Divider 1 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Rev. A | Page 57 of 64
AD9518-0