AD9518-3A/PCBZ Analog Devices Inc, AD9518-3A/PCBZ Datasheet - Page 51
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AD9518-3A/PCBZ
Manufacturer Part Number
AD9518-3A/PCBZ
Description
6-Output Clock Generator With 2.8GHz
Manufacturer
Analog Devices Inc
Datasheet
1.AD9518-3ABCPZ-RL7.pdf
(64 pages)
Specifications of AD9518-3A/PCBZ
Main Purpose
Timing, Clock Generator
Embedded
No
Utilized Ic / Part
AD9518-3A
Primary Attributes
2 Inputs, 6 Outputs, 2.0GHz VCO
Secondary Attributes
LVPECL Output Logic
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Reg.
Addr.
(Hex)
0x01A
Bits
[6]
[5:0]
Name
Reference
frequency monitor
threshold
LD pin control
Description
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO
frequency monitor’s detection threshold (see
0: frequency valid if frequency is above the higher frequency threshold (default).
1: frequency valid if frequency is above the lower frequency threshold.
Selects the signal that is connected to the LD pin.
5
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
0
0
0
0
0
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
2
0
0
0
0
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rev. A | Page 51 of 64
Level or
Dynamic
Signal
LVL
DYN
DYN
HIZ
CUR
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
DYN
DYN
DYN
DYN
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
LVL
Table 15
Signal at LD Pin
Digital lock detect (high = lock, low = unlock) (default).
P-channel, open-drain lock detect (analog lock detect).
N-channel, open-drain lock detect (analog lock detect).
High-Z LD pin.
Current source lock detect (110 μA when DLD is true).
Ground (dc); for all other cases of 0XXXXX not specified above.
The selections that follow are the same as REFMON.
Ground (dc).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in differential mode).
Unselected reference to PLL (not available in differential mode).
Status of selected reference (status of differential reference); active high.
Status of unselected reference (not available in differential mode); active
high.
Status REF1 frequency; active high.
Status REF2 frequency; active high.
(Status REF1 frequency) AND (status REF2 frequency).
(DLD) AND (status of selected reference) AND (status of VCO).
Status of VCO frequency (active high).
Selected reference (low = REF1, high = REF2).
Digital lock detect (DLD); active high.
Holdover active; active high.
Not available. Do not use.
VS (PLL supply).
REF1 clock (differential reference when in differential mode).
REF2 clock (not available in differential mode).
Selected reference to PLL (differential reference when in differential mode).
Unselected reference to PLL (not available in differential mode).
Status of selected reference (status of differential reference); active low.
Status of unselected reference (not available in differential mode); active
low.
Status of REF1 frequency; active low.
Status of REF2 frequency; active low.
(Status of REF1 frequency) AND (status of REF2 frequency) .
(DLD) AND (status of selected reference) AND (status of VCO) .
Status of VCO frequency; active low.
Selected reference (low = REF2, high = REF1).
Digital lock detect (DLD); active low.
Holdover active; active low.
Not available. Do not use.
, REF1, REF2, and VCO frequency status monitor).
AD9518-3