AD9520-0BCPZ Analog Devices Inc, AD9520-0BCPZ Datasheet - Page 75

• Manufacturer Part Number: AD9520-0BCPZ
• Description: Clock IC With 2.8GHz On-chip VCO
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-0BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.95GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.95GHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
01F
01F
01F
Table 54. Output Driver Control
Reg.
Addr
(Hex) Bit(s) Name
0F0
0F0
0F0
0F0
0F0
0F1
0F2
0F3
0F4
0F5
[2]
[1]
[0]
[7]
[6:5]
[4:3]
[2:1]
[0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
REF2 frequency
> threshold
(read-only)
REF1 frequency
> threshold
(read-only)
Digital lock
detect
(read-only)
OUT0 format
OUT0 CMOS
configuration
OUT0 polarity
OUT0 LVPECL
differential
voltage
OUT0 LVPECL
power-down
OUT1 control
OUT2 control
OUT3 control
OUT4 control
OUT5 control
Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x01A[6].
[2] = 0; REF2 frequency is less than the threshold frequency.
[2] = 1; REF2 frequency is greater than the threshold frequency.
Readback register. Indicates if the frequency of the signal at REF1 is greater than the threshold frequency
set by Register 0x01A[6].
[1] = 0; REF1 frequency is less than the threshold frequency.
[1] = 1; REF1 frequency is greater than the threshold frequency.
Readback register. Digital lock detect.
[0] = 0; PLL is not locked.
[0] = 1; PLL is locked.
Description
Selects the output type for OUT0.
Description
[7] = 0; LVPECL (default).
[7] = 1; CMOS.
Sets the CMOS output configuration for OUT0 when 0x0F0[7] = 1.
[6:5]
00
01
10
11 (default)
Sets the output polarity for OUT0.
[7]
0 (default)
0
1
1
1
1
Sets the LVPECL output differential voltage (V
[2]
0
0
1 (default)
1
LVPECL power-down.
[0] = 0; normal operation (default).
[0] = 1; safe power-down.
This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0.
OUT0A
Tristate
On
Tristate
On
[4]
X
X
0 (default)
0
1
1
[1]
0
1
0 (default)
1
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OUT0B
Tristate
Tristate
On
On
[3]
0 (default)
1
0
1
0
1
V
400
600
780
960
OD
(mV)
OD
).
Output Type
LVPECL
LVPECL
CMOS
CMOS
CMOS
CMOS
OUT0A
Noninverting
Inverting
Noninverting
Inverting
Noninverting
Inverting
Inverting
Noninverting
Noninverting
Inverting
Noninverting
OUT 0B
Inverting
AD9520-0