AD9520-2BCPZ-REEL7 Analog Devices Inc, AD9520-2BCPZ-REEL7 Datasheet - Page 24

12/24 Channel Clock Distribution W/ On-C

AD9520-2BCPZ-REEL7

Manufacturer Part Number
AD9520-2BCPZ-REEL7
Description
12/24 Channel Clock Distribution W/ On-C
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet

Specifications of AD9520-2BCPZ-REEL7

Design Resources
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVPECL
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.33GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
2.33GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9520-2
Figure 24. Internal VCO Phase Noise (Absolute), Direct-to-LVPECL @ 2175 MHz
Figure 25. Internal VCO Phase Noise (Absolute), Direct-to-LVPECL @ 2335 MHz
–100
–110
–120
–130
–140
–150
–100
–110
–120
–130
–140
–150
–100
–110
–120
–130
–140
–150
–160
–40
–50
–60
–70
–80
–90
–40
–50
–60
–70
–80
–90
Figure 26. Additive (Residual) Phase Noise, CLK-to-LVPECL @
1k
1k
10
100
10k
10k
245.76 MHz, Divide-by-1
1k
100k
FREQUENCY (Hz)
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
10k
100k
1M
1M
1M
10M
10M
10M
100M
100M
100M
Rev. 0 | Page 24 of 84
–100
–110
–120
–130
–140
–150
–160
–100
–110
–120
–130
–140
–150
–160
–110
–120
–130
–140
–150
–160
–170
Figure 27. Additive (Residual) Phase Noise, CLK-to-LVPECL @
Figure 28. Additive (Residual) Phase Noise, CLK-to-LVPECL @
Figure 29. Additive (Residual) Phase Noise, CLK-to-CMOS @
10
10
10
100
100
100
1k
1k
1k
1600 MHz, Divide-by-1
200 MHz, Divide-by-5
50 MHz, Divide-by-20
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
10k
10k
10k
100k
100k
100k
1M
1M
1M
10M
10M
10M
100M
100M
100M

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