AD9520-4BCPZ-REEL7 Analog Devices Inc, AD9520-4BCPZ-REEL7 Datasheet - Page 79
![Clock IC With 1.6GHz On-chip VCO](/photos/6/50/65021/505-64-lfcsp_sml.jpg)
AD9520-4BCPZ-REEL7
Manufacturer Part Number
AD9520-4BCPZ-REEL7
Description
Clock IC With 1.6GHz On-chip VCO
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9520-4BCPZ-REEL7.pdf
(84 pages)
Specifications of AD9520-4BCPZ-REEL7
Design Resources
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVPECL
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
1.8GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
1.8GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AD9520-4/PCBZ - BOARD EVAL FOR AD9520-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Reg.
Addr
(Hex) Bit(s) Name
19B
Reg.
Addr
(Hex) Bit(s) Name
1E0
1E1
1E1
1E1
1E1
1E1
Table 56. VCO Divider and CLK Input
[2:0] VCO divider
[4]
[3]
[2]
[1]
[0]
[0]
Power-down clock input section Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
Power-down VCO clock interface Powers down the interface block between VCO and clock distribution.
Power-down VCO and CLK
Select VCO or CLK
Bypass VCO divider
Disable Divider 3 DCC
Description
Duty-cycle correction function.
[0] = 0; enable duty-cycle correction (default).
[0] = 1; disable duty-cycle correction.
Description
[2]
0
0
0
0
1
1
1
1
[4] = 0; normal operation (default).
[4] = 1; power down.
[3] = 0; normal operation (default).
[3] = 1; power down.
Powers down both VCO and CLK input.
[2] = 0; normal operation (default).
[2] = 1; power down.
Selects either the VCO or the CLK as the input to VCO divider.
[1] = 0; select external CLK as input to VCO divider (default).
[1] = 1; select VCO as input to VCO divider; cannot bypass VCO divider when this is
selected. This bit must be set to use the PLL with the internal VCO.
Bypasses or uses the VCO divider.
[0] = 0; use VCO divider (default).
[0] = 1; bypass VCO divider; cannot select VCO as input when this is selected.
Rev. 0 | Page 79 of 84
[1]
0
0
1
1
0
0
1
1
[0]
0
1
0
1
0
1
0
1
Divide
2 (default)
3
4
5
6
Output static
1 (bypass)
Output static
AD9520-4