AD9520-5/PCBZ Analog Devices Inc, AD9520-5/PCBZ Datasheet - Page 56

• Manufacturer Part Number: AD9520-5/PCBZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc

Specifications of AD9520-5/PCBZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: AD9520-5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Compliant

AD9520-5
REGISTER MAP
Register addresses that are not listed in Table 44 are not used, and writing to those registers has no effect. The user should avoid writing
values other than 00h to register addresses marked unused.
Table 44. Register Map Overview
Addr
(Hex)
Serial Port Configuration
000
001
002
003
004
EEPROM ID
005
006
007
to
00F
PLL
010
011
012
013
014
015
016
017
018
019
01A
01B
01C
01D
Parameter
Serial port
config
(SPI mode)
Serial port
config
(I²C mode)
Readback
control
EEPROM
customer
version ID
PFD charge
pump
R counter
A counter
B counter
PLL_CTRL_1
PLL_CTRL_2
PLL_CTRL_3
PLL_CTRL_4
PLL_CTRL_5
PLL_CTRL_6
PLL_CTRL_7
PLL_CTRL_8
Bit 7 (MSB)
SDO active
Set CP pin
to VCP/2
Enable CMOS
reference
input
dc offset
Enable
STATUS
pin divider
Enable CLK
frequency
monitor
Disable
switchover
deglitch
Enable
Status_EEPROM
at STATUS pin
PFD polarity
R, A, B counters
SYNC pin reset
Unused
Unused
Unused
Unused
Bit 6
addr incr
Ref freq
monitor
threshold
Select
REF2
Enable
XTAL
OSC
LSB first/
Reset
R counter
Enable
REF2
( REFIN )
frequency
monitor
Lock detect
counter
Charge pump current
Bit 5
Soft reset
(self-
clearing)
Soft reset
(self-
clearing)
Reset
A and B
counters
Enable
REF1
(REFIN)
frequency
monitor
Use
REF_SEL
pin
Enable
clock
doubler
STATUS pin control
Rev. 0 | Page 56 of 80
EEPROM customer version ID (MSB)
EEPROM customer version ID (LSB)
Bit 4
Unused
Unused
Reset all
counters
Digital
lock
detect
window
Enable
automatic
reference
switchover
Disable
PLL status
register
14-bit R counter, Bits[7:0] (LSB)
13-bit B counter, Bits[7:0] (LSB)
R path delay
Unused
Reserved (read-only)
Reserved (read-only)
Unused
Unused
Bit 3
Unused
Unused
B counter
bypass
Disable
digital
lock
detect
Stay on REF2
Enable
LD pin
comparator
14-bit R counter, Bits[13:8] (MSB)
Charge pump mode
13-bit B counter, Bits[12:8] (MSB)
6-bit A counter
LD pin control
REFMON pin control
Bit 2
Soft reset
(self-
clearing)
Soft reset
(self-
clearing)
Enable
REF2
Unused
Bit 1
Enable
LSB first/
addr incr
Enable
REF1
external
holdover
N path delay
Antibacklash pulse width
Prescaler P
Unused
PLL power-down
Unused
Bit 0 (LSB)
SDO active
Readback
active regs
Enable
differential
reference
Enable
holdover
Default
Value
(Hex)
00
00
N/A
N/A
N/A
00
00
00
7D
01
00
00
03
00
06
00
06
00
00
00
00
80
00