AD9520-5BCPZ-REEL7 Analog Devices Inc, AD9520-5BCPZ-REEL7 Datasheet - Page 11
![12/24-Output Clock Generator](/photos/6/50/65021/505-64-lfcsp_sml.jpg)
AD9520-5BCPZ-REEL7
Manufacturer Part Number
AD9520-5BCPZ-REEL7
Description
12/24-Output Clock Generator
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet
1.AD9520-5BCPZ.pdf
(80 pages)
Specifications of AD9520-5BCPZ-REEL7
Design Resources
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVPECL
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.4GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
1.6GHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 7.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 8.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CMOS OUTPUT ADDITIVE TIME JITTER
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
CLK = 622.08 MHz
CLK = 622.08 MHz
CLK = 1000 MHz
CLK = 500 MHz
CLK = 200 MHz
Any LVPECL Output = 622.08 MHz
Divide Ratio = 1
Any LVPECL Output = 155.52 MHz
Divide Ratio = 4
Any LVPECL Output = 100 MHz
Divide Ratio = 10
Any LVPECL Output = 100 MHz
Divide Ratio = 5
Any CMOS Output Pair = 100 MHz
Divide Ratio = 2
Min
Min
Typ
46
64
223
209
325
54
79
124
Typ
77
109
114
163
176
259
Rev. 0 | Page 11 of 80
Max
Max
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Unit
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Unit
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Test Conditions/Comments
Application example based on a typical setup using an
external 245.76 MHz VCXO (Toyocom TCO-2112);
reference = 15.36 MHz; R DIV = 1
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Distribution section only; does not include the PLL;
measured at rising edge of clock signal
Integration bandwidth = 12 kHz to 20 MHz
Integration bandwidth = 12 kHz to 20 MHz
Calculated from SNR of ADC method
Broadband jitter
Calculated from SNR of ADC method
Broadband jitter
Distribution section only; does not include the PLL
Calculated from SNR of ADC method
Broadband jitter
AD9520-5