AD9640ABCPZ-105 Analog Devices Inc, AD9640ABCPZ-105 Datasheet - Page 15
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AD9640ABCPZ-105
Manufacturer Part Number
AD9640ABCPZ-105
Description
14Bit 105Msps Dual 1.8V PB Free ADC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9640ABCPZ-80.pdf
(52 pages)
Specifications of AD9640ABCPZ-105
Design Resources
Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
Number Of Bits
14
Sampling Rate (per Second)
105M
Data Interface
Serial, SPI™
Number Of Converters
2
Power Dissipation (max)
657mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9640ABCPZ-105
Manufacturer:
ADI/亚德诺
Quantity:
20 000
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 11. Pin Function Descriptions (Parallel CMOS Mode)
Pin No.
ADC Power Supplies
20, 64
1, 21
24, 57
36, 45, 46
0
ADC Analog
37
38
44
43
39
40
42
41
49
50
Mnemonic
DRGND
DRVDD
DVDD
AVDD
AGND,
Exposed Pad
VIN+A
VIN−A
VIN+B
VIN−B
VREF
SENSE
RBIAS
CML
CLK+
CLK−
D13B (MSB)
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE
D0A (LSB)
ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
DRVDD
Type
Ground
Supply
Supply
Supply
Ground
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
DCOB
DCOA
D10B
D11B
D12B
D6B
D7B
D8B
D9B
D1A
D2A
D3A
D4A
10
12
13
14
15
16
11
Figure 6. Pin Configuration, LFCSP Parallel CMOS (Top View)
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
Description
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
The exposed thermal pad on the bottom of the package provides the analog ground
for the part. This exposed pad must be connected to ground for proper operation.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 14 for details.
External Reference Bias Resistor.
Common Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
PARALLEL CMOS
Rev. B | Page 15 of 52
(Not to Scale)
AD9640
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
AD9640