AD9640ABCPZ-125 Analog Devices Inc, AD9640ABCPZ-125 Datasheet - Page 34
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AD9640ABCPZ-125
Manufacturer Part Number
AD9640ABCPZ-125
Description
14Bit 125Msps Dual 1.8V PB Free ADC
Manufacturer
Analog Devices Inc
Datasheet
1.AD9640ABCPZ-80.pdf
(52 pages)
Specifications of AD9640ABCPZ-125
Design Resources
Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
Number Of Bits
14
Sampling Rate (per Second)
125M
Data Interface
Serial, SPI™
Number Of Converters
2
Power Dissipation (max)
846mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD9640ABCPZ-125
Manufacturer:
ADI
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Part Number:
AD9640ABCPZ-125
Manufacturer:
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Quantity:
20 000
AD9640
similarly, corresponds to the fine lower threshold bits, except
that it is asserted only if the input magnitude is less than the
value programmed in the fine lower threshold register after the
dwell time elapses. The dwell time is set by the 16-bit dwell time
value located at Address 0x10A and Address 0x10B and is set in
units of ADC input clock cycles ranging from 1 to 65,535. The
fine lower threshold register is a 13-bit register that is compared
with the magnitude at the output of the ADC. This comparison
is subject to the ADC clock latency but allows a finer, more
accurate comparison. The fine upper threshold magnitude is
defined by the following equation:
F_UT
F_LT
Figure 67. Threshold Settings for F_UT and F_LT
Rev. B | Page 34 of 52
The decrement gain output works from the ADC fast detect
output pins, providing a fast indication of potential overrange
conditions. The increment gain uses the comparison at the
output of the ADC, requiring the input magnitude to remain
below an accurate, programmable level for a predefined period
before signaling external circuitry to increase the gain.
The operation of the increment gain output and the decrement
gain output is shown in Figure 67.
dBFS = 20 log(Threshold Magnitude/2
FINE LOWER THRESHOLD
FINE UPPER THRESHOLD
13
)