AD974AR Analog Devices Inc, AD974AR Datasheet - Page 11

• Manufacturer Part Number: AD974AR
• Description: A/D Converter (A-D) IC
• Manufacturer: Analog Devices Inc
• Type: Data Acquisition System (DAS)r

Specifications of AD974AR

• Package/case: 28-SOIC
• Features: 4?Ch., 200kSPS Data Acquisition System
• Interface Type: Serial
• Number Of Bits: 16
• Number Of Channels: 4
• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Resolution (bits): 16 b
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Voltage Supply Source: Analog and Digital
• Voltage - Supply: 5V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-AD974CB - BOARD EVAL FOR AD974
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

EXTERNAL CONTINUOUS CLOCK DATA READ AFTER
CONVERSION WITH SYNC OUTPUT GENERATED
Figure 8 illustrates the method by which data from conversion
“n” can be read after the conversion is complete using a con-
tinuous external clock, with the generation of a SYNC output.
What permits the generation of a SYNC output is a transition of
DATACLK either while CS is high or while both CS and R/C are
low.
With a continuous clock the CS pin cannot be tied low as it
could be with a discontinuous clock. Use of a continuous clock,
while a conversion is occurring, can increase the DNL and
Transition Noise of the AD974.
After a conversion is complete, indicated by BUSY returning
high, the result of that conversion can be read while CS is low
REV. A
Figure 8. Conversion and Read Timing Using an External Continuous Data Clock (EXT/ INT Set to Logic High)
DATACLK
BUSY
SYNC
DATA
EXT
R/C
CS
t
t
1
2
t
10
t
13
t
15
0
t
17
t
12
1
t
14
t
t
16
12
2
–11–
BIT 15
(MSB)
t
and R/C is high. In Figure 8 clock pulse #0 is used to enable the
generation of a SYNC pulse. The SYNC pulse is actually clocked
out approximately 40 ns after the rising edge of clock pulse #1.
The SYNC pulse will be valid on the falling edge of clock pulse
#1 and the rising edge of clock pulse #2. The MSB will be valid
on the falling edge of clock pulse #2 and the rising edge of clock
pulse #3. The LSB will be valid on the falling edge of clock
pulse #17 and the rising edge of clock pulse #18.
When reading data after the conversion is complete, with the
highest frequency permitted for DATACLK (15.15 MHz) the
maximum possible throughput is approximately 195 kHz and
not the rated 200 kHz.
18
3
BIT 14
4
17
(LSB)
BIT 0
18
t
19
t
18
AD974