AD9762-EBZ Analog Devices Inc, AD9762-EBZ Datasheet - Page 11

• Manufacturer Part Number: AD9762-EBZ
• Description: 12-BIT 100 MSPS+ TxDAC D/A Converter
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9762-EBZ

• Number Of Dac's: 1
• Number Of Bits: 12
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 125M
• Data Interface: Parallel
• Settling Time: 35ns
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9762
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FUNCTIONAL DESCRIPTION
Figure 39 shows a simplified block diagram of the AD9762.
The AD9762 consists of a large PMOS current source array
that is capable of providing up to 20 mA of total current. The
array is divided into 31 equal currents that make up the 5
most significant bits (MSBs). The next 4 bits or middle bits
consist of 15 equal current sources whose value is 1/16th of an
MSB current source. The remaining LSBs are binary weighted
fractions of the middle-bits current sources. Implementing
the middle and lower bits with current sources, instead of an
R-2R ladder, enhances its dynamic performance for multitone
or low amplitude signals and helps maintain the DAC’s high
output impedance (i.e., >100 kΩ).
All of these current sources are switched to one or the other
of the two output nodes (i.e., I
tial current switches. The switches are based on a new archi-
tecture that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the
differential current switches.
The analog and digital sections of the AD9762 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 volt to 5.5 volt range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V bandgap
voltage reference and a reference control amplifier.
The full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, R
with both the reference control amplifier and voltage refer-
ence V
over to the segmented current sources with the proper scaling
factor. The full-scale current, I
of I
DAC TRANSFER FUNCTION
The AD9762 provides complementary current outputs, I
and I
I
I
current output appearing at I
both the input code and I
REV. B
OUTFS
OUTB
REF
OUTB
, the complementary output, provides no current. The
.
, when all bits are high (i.e., DAC CODE = 4095) while
REFIO
. I
, sets the reference current I
OUTA
0.1 F
will provide a near full-scale current output,
SET
CLOCK
. The external resistor, in combination
V
R
REFIO
2k
OUTFS
SET
OUTA
OUTA
OUTFS
and can be expressed as:
+5V
I
REF
or I
and I
, is thirty-two times the value
OUTB
REFIO
FS ADJ
DVDD
DCOM
CLOCK
OUTB
REF
SLEEP
+1.20V REF
) via PMOS differen-
, which is mirrored
is a function of
REFLO
Figure 39. Functional Block Diagram
SEGMENTED SWITCHES
FOR DB11–DB3
DIGITAL DATA INPUTS (DB11–DB0)
50pF
OUTA
LATCHES
COMP1
CURRENT SOURCE
0.1 F
–11–
ARRAY
PMOS
where DAC CODE = 0 to 4095 (i.e., Decimal Representation).
As mentioned previously, I
current I
V
where I
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, I
and I
loads, R
R
I
50 Ω or 75 Ω cable. The single-ended voltage output appearing
at the I
Note the full-scale value of V
the specified output compliance range to maintain specified
distortion and linearity performance.
The differential voltage, V
I
Substituting the values of I
expressed as:
These last two equations highlight some of the advantages of
operating the AD9762 differentially. First, the differential
operation will help cancel common-mode error sources associated
with I
Second, the differential code dependent current and subsequent
voltage, V
output (i.e., V
power to the load.
Note, the gain drift temperature performance for a single-ended
(V
can be enhanced by selecting temperature tracking resistors for
R
in Equation 8.
+5V
OUTA
OUTB
REFIO
LOAD
LOAD
AVDD
SWITCHES
V
V
OUTA
OUTA
OUTB
I
I
I
V
V
(32 R
LSB
OUTA
OUTB
OUTFS
OUTB
OUTA
is:
DIFF
DIFF
or I
may represent the equivalent load resistance seen by
and R
and external resistor R
OUTA
REF
and V
LOAD
= I
REF
= I
OUTB
DIFF
LOAD
= (DAC CODE/4096) × I
= (4095 – DAC CODE)/4096 × I
= (I
= {(2 DAC CODE – 4095)/4096} ×
should be directly connected to matching resistive
AD9762
= V
= 32 × I
ACOM
and I
OUTA
OUTB
, which is nominally set by a reference voltage
and I
, which are tied to analog common, ACOM. Note,
SET
, is twice the value of the single-ended voltage
OUTB
OUTA
OUTA
COMP2
/R
IOUTA
IOUTB
REFIO
as would be the case in a doubly terminated
due to their ratiometric relationship as shown
SET
× R
OUTB
× R
OUTB
) or differential output (V
REF
– I
or V
) × V
/R
LOAD
LOAD
0.1 F
SET
OUTB
I
such as noise, distortion and dc offsets.
OUTB
nodes is simply :
OUTB
REFIO
DIFF
OUTFS
) × R
OUTA
I
OUTA
), thus providing twice the signal
OUTA
SET
, appearing across I
V
, I
DIFF
LOAD
V
R
50
. It can be expressed as:
is a function of the reference
OUTB
LOAD
OUTB
and V
= V
OUTFS
OUTA
, and I
OUTB
– V
V
R
50
DIFF
OUTA
OUTFS
OUTB
LOAD
REF
should not exceed
) of the AD9762
AD9762
; V
OUTA
DIFF
and
can be
OUTA
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)