AD9772A-EBZ Analog Devices Inc, AD9772A-EBZ Datasheet - Page 17

• Manufacturer Part Number: AD9772A-EBZ
• Description: 14Bit 160 MSPS TxDAC+ W/2X Interpolation
• Manufacturer: Analog Devices Inc
• Series: TxDAC+®r

Specifications of AD9772A-EBZ

• Number Of Dac's: 1
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 160M
• Data Interface: Parallel
• Settling Time: 11ns
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9772A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
FUNCTIONAL DESCRIPTION
Figure 26 shows a simplified block diagram of the AD9772A.
The AD9772A is a complete 2× oversampling, 14-bit DAC that
includes a 2× interpolation filter, a phase-locked loop (PLL)
clock multiplier, and a 1.20 V band gap voltage reference.
Although the AD9772A digital interface can support input data
rates as high as 160 MSPS, its internal DAC can operate up to
400 MSPS, thus providing direct IF conversion capabilities.
The 14-bit DAC provides two complementary current outputs
whose full-scale current is determined by an external resistor.
The AD9772A features a flexible, low jitter differential clock
input, providing excellent noise rejection while accepting a sine
wave input. An on-chip PLL clock multiplier produces all of the
necessary synchronized clocks from an external reference clock
source. Separate supply inputs are provided for each functional
block to ensure optimum noise and distortion performance. A
sleep mode is also included for power savings.
(DB13 TO
Preceding the 14-bit DAC is a 2× digital interpolation filter that
can be configured for a low-pass (that is, baseband mode) or
high-pass (that is, direct IF mode) response. The input data is
latched into the edge-triggered input latches on the rising edge
of the differential input clock, as shown in Figure 2, and then
interpolated by a factor of 2 by the digital filter. For traditional
baseband applications, the 2× interpolation filter has a low-pass
response. For direct IF applications, the filter response can be
converted into a high-pass response to extract the higher image.
The output data of the 2× interpolation filter can update the
14-bit DAC directly or undergo a zero-stuffing process to increase
the DAC update rate by another factor of 2. This action enhances
the relative signal level and pass-band flatness of the higher
frequency images.
DIGITAL MODES OF OPERATION
The AD9772A features four modes of operation controlled by
the digital inputs, MOD0 and MOD1. MOD0 controls the 2×
digital filter response (that is, low-pass or high-pass), and
MOD1 controls the zero-stuffing option. The appropriate mode
to select (see Table 9) depends on whether the application
requires the reconstruction of a baseband or IF signal.
INPUTS
SLEEP
DATA
CLK+
CLK–
DB0)
CLKCOM CLKVDD MOD0 MOD1 RESET PLLLOCK DIV0 DIV1
DCOM DVDD
TRIGGERED
LATCHES
Figure 26. Simplified Functional Block Diagram
1×
EDGE-
AD9772A
1× /2×
CLOCK DISTRIBUTION
CONTROL
AND MODE SELECT
POLATION
ACOM AVDD
FILTER
FILTER
INTER-
2× FIR
CONTROL
MUX
STUFF
ZERO
MUX
AND CONTROL AMP
1.2V REFERENCE
2× /4×
PLL CLOCK
MULTIPLIER
14-BIT DAC
REFLO
I
REFIO
FSADJ
PLLCOM
LPF
PLLVDD
I
OUTA
OUTB
Rev. C | Page 17 of 40
Table 9. Digital Modes
Digital
Mode
Baseband
Baseband
Direct IF
Direct IF
For applications requiring the highest dynamic range over a
wide bandwidth, users should consider operating the AD9772A
in a baseband mode. Although the zero-stuffing option can be
used in this mode, the ratio of the signal to the image power
will be reduced.
For applications requiring the synthesis of IF signals, users
should consider operating the AD9772A in a direct IF mode. In
this case, the zero-stuffing option should be considered when
synthesizing and selecting IFs beyond the input data rate, f
If the reconstructed IF falls below f
may or may not be beneficial. Note that the dynamic range (that
is, SNR/SFDR) can be optimized by disabling the PLL clock
multiplier (that is, by connecting PLLVDD to PLLCOM) and by
using an external low-jitter clock source operating at the DAC
update rate, f
2× Interpolation Filter Description
The 2× interpolation filter is based on a 43-tap, half-band,
symmetric FIR topology that can be configured for a low- or
high-pass response, depending on the state of the MOD0
control input. The low-pass response is selected with MOD0
low, and the high-pass response is selected with MOD0 high.
The low-pass frequency and the impulse response of the half-
band interpolation filter are shown in Figure 4 and Figure 5,
and the idealized filter coefficients are listed in Table 5. Note
that the impulse response of a FIR filter is also represented by
its idealized filter coefficients.
The 2× interpolation filter essentially multiplies the input data rate
to the DAC by a factor of 2, relative to its original input data rate,
while reducing the magnitude of the first image associated with
the original input data rate occurring at f
result of the 2× interpolation, the digital filter frequency response is
uniquely defined over its Nyquist zone of dc to f
images occurring in adjacent Nyquist zones.
The benefits of an interpolation filter are clearly seen in
Figure 27, which shows an example of the frequency and time
domain representation of a discrete time sine wave signal before
and after it is applied to the 2× digital interpolation filter in a
low-pass configuration. Images of the sine wave signal appear
around multiples of the input data rate (that is, f
as predicted by sampling theory. These undesirable images also
appear at the output of a reconstruction DAC, although they are
attenuated by the sin(x)/x roll-off response of the DAC.
DAC
MOD0
0
0
1
1
.
MOD1
0
1
0
1
DATA
Digital
Filter
Low
Low
High
High
, the zero-stuffing option
DATA
− f
DATA
DATA
FUNDAMENTAL
AD9772A
, with mirror
) of the DAC,
Zero-
Stuffing
No
Yes
No
Yes
DATA
. As a
.