AD9835BRU-REEL7 Analog Devices Inc, AD9835BRU-REEL7 Datasheet - Page 14

• Manufacturer Part Number: AD9835BRU-REEL7
• Description: IC,Numeric-Controlled Oscillator,CMOS,TSSOP,16PIN,PLASTIC
• Manufacturer: Analog Devices Inc

Specifications of AD9835BRU-REEL7

• Rohs Status: RoHS non-compliant
• Resolution (bits): 10 b
• Master Fclk: 50MHz
• Tuning Word Width (bits): 32 b
• Voltage - Supply: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• For Use With: EVAL-AD9835EBZ - BOARD EVALUATION FOR AD9835

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AD9835
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. In order to load data into the AD9835,
PC7 is held low after the first eight bits are transferred and a
second serial write operation is performed to the AD9835. Only
after the second eight bits have been transferred should FSYNC
be taken high again.
AD9835-to-80C51/80L51 Interface
Figure 26 shows the serial interface between the AD9835 and
the 80C51/80L51 microcontroller. The microcontroller is oper-
ated in Mode 0 so that TXD of the 80C51/80L51 drives SCLK
of the AD9835 while RXD drives the serial data line SDATA.
The FSYNC signal is again derived from a bit programmable
pin on the port (P3.3 being used in the diagram). When data is
to be transmitted to the AD9835, P3.3 is taken low. The
80C51/80L51 transmits data in 8-bit bytes thus, only eight
falling SCLK edges occur in each cycle. To load the remaining
eight bits to the AD9835, P3.3 is held low after the first eight
bits have been transmitted and a second write operation is initi-
ated to transmit the second byte of data. P3.3 is taken high
following the completion of the second write operation. SCLK
should idle high between the two write operations. The 80C51/
80L51 outputs the serial data in a format which has the LSB
first. The AD9835 accepts the MSB first (the 4 MSBs being the
control information, the next 4 bits being the address while the
8 LSBs contain the data when writing to a destination register).
Therefore, the transmit routine of the 80C51/80L51 must take
this into account and rearrange the bits so that the MSB is out-
put first.
AD9835-to-DSP56002 Interface
Figure 27 shows the interface between the AD9835 and the
DSP56002. The DSP56002 is configured for normal mode
asynchronous operation with a Gated internal clock (SYN = 0,
GCK = 1, SCKD = 1). The frame sync pin is generated inter-
nally (SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0
= 0) and the frame sync signal will frame the 16 bits (FSL = 0).
Figure 25. 68HC11/68L11-to-AD9835 Interface
Figure 26. 80C51/80L51 to AD9835 Interface
ADDITIONAL PINS OMITTED FOR CLARITY
ADDITIONAL PINS OMITTED FOR CLARITY
68HC11/68L11
80C51/80L51
MOSI
SCK
PC7
P3.3
RXD
TXD
FSYNC
SDATA
SCLK
FSYNC
SDATA
SCLK
AD9835
AD9835
–14–
The frame sync signal is available on pin SC2 but, it needs to be
inverted before being applied to the AD9835. The interface to
the DSP56000/DSP56001 is similar to that of the DSP56002.
AD9835 Evaluation Board
The AD9835 Evaluation Board allows designers to evaluate the
high performance AD9835 DDS Modulator with a minimum of
effort.
To prove that this device will meet the user’s waveform synthe-
sis requirements, the user only requires a 5 V power supply, an
IBM-compatible PC and a spectrum analyzer along with the
evaluation board. The evaluation setup is shown below.
The DDS Evaluation kit includes a populated, tested AD9835
printed circuit board along with the software that controls the
AD9835 in a Windows
Using the AD9835 Evaluation Board
The AD9835 Evaluation kit is a test system designed to simplify
the evaluation of the AD9835. Provisions to control the AD9835
from the printer port of an IBM-compatible PC are included
along with the necessary software. An application note is also
available with the evaluation board which gives information on
operating the evaluation board.
Prototyping Area
An area is available on the evaluation board where the user can
add additional circuits to the evaluation test set. Users may
want to build custom analog filters for the output or add buffers
and operational amplifiers to be used in the final application.
XO vs. External Clock
The AD9835 can operate with master clocks up to 50 MHz. A
50 MHz oscillator is included on the evaluation board. How-
ever, this oscillator can be removed and an external CMOS
clock connected to the part, if required.
Power Supply
Power to the AD9835 Evaluation Board must be provided ex-
ternally through the pin connections. The power leads should be
twisted to reduce ground loops.
AD9835.EXE
Figure 28. AD9835 Evaluation Board Setup
Figure 27. AD9835-to-DSP56002 Interface
ADDITIONAL PINS OMITTED FOR CLARITY
DSP56002
IBM-COMPATIBLE PC
SCK
STD
SC2
®
environment.
PARALLEL PORT
PRINTER CABLE
CENTRONICS
FSYNC
SDATA
SCLK
AD9835
AD9835 EVALUATION
BOARD
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