AD9985ABSTZ-110 Analog Devices Inc, AD9985ABSTZ-110 Datasheet
AD9985ABSTZ-110
Specifications of AD9985ABSTZ-110
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AD9985ABSTZ-110 Summary of contents
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FEATURES Automated clamping level adjustment 140 MSPS maximum conversion rate 300 MHz analog bandwidth 0 1.0 V analog input range 500 ps p-p PLL clock jitter at 110 MSPS 3.3 V power supply Full sync processing Sync detect ...
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AD9985 TABLE OF CONTENTS Revision History ........................................................................... 2 Specifications..................................................................................... 3 Explanation of Test Levels........................................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Design Guide................................................................................... 11 General Description................................................................... 11 Digital Inputs .............................................................................. 11 Input Signal ...
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SPECIFICATIONS Analog Interface 3 3.3 V, ADC clock = maximum conversion rate, unless otherwise noted Table 1. Parameter Temp RESOLUTION DC ACCURACY Differential Nonlinearity 25°C Full Integral Nonlinearity 25°C Full No Missing Codes ...
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AD9985 Parameter Temp DIGITAL OUTPUTS Output Voltage, High (V ) Full OH Output Voltage, Low (V ) Full OL Duty Cycle DATACK Full Output Coding POWER SUPPLY V Supply Voltage Full D V Supply Voltage Full DD P Supply Voltage ...
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Table 2. Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity ANALOG INPUT Input Voltage Range Minimum Maximum Gain Tempco Input Bias Current Input Offset Voltage Input Full-Scale Matching Offset Adjustment Range REFERENCE OUTPUT Output Voltage Temperature Coefficient SWITCHING PERFORMANCE Maximum ...
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AD9985 Parameter POWER SUPPLY V Supply Voltage D V Supply Voltage DD P Supply Voltage VD I Supply Current ( Supply Current ( Supply Current ( Total Power ...
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ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Analog Inputs VREF IN Digital Inputs Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high ...
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AD9985 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND GREEN <7> GREEN <6> GREEN <5> GREEN <4> GREEN <3> GREEN <2> GREEN <1> GREEN <0> GND BLUE <7> BLUE <6> BLUE <5> BLUE <4> BLUE <3> BLUE <2> BLUE <1> BLUE <0> ...
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Table 5. Pin Function Descriptions Pin Function Name OUTPUTS HSOUT Horizontal Sync Output A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be programmed via serial bus registers. By maintaining alignment ...
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AD9985 Pin Function Name SOGIN Sync-on-Green Input This input is provided to assist with processing signals with embedded sync, typically on the Green channel. The pin is connected to a high speed comparator with an internally generated threshold. The threshold ...
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DESIGN GUIDE GENERAL DESCRIPTION The AD9985 is a fully integrated solution for capturing analog RGB signals and digitizing them for display on flat-panel monitors or projectors. The circuit is ideal for providing a computer interface for HDTV monitors or as ...
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AD9985 input is present. The offset then remains in place when other signal levels are processed, and the entire signal is shifted to eliminate offset errors. In most PC graphics systems, black is transmitted between active video lines. With CRT ...
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ADC channels as well as any offset errors present on the incoming graphics or video signals. To activate the auto-offset mode, set Register 1Dh, Bit Next, the target code registers (19h through ...
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AD9985 100 110 120 130 140 150 FREQUENCY (MHz) Figure 7. Pixel Clock Jitter vs. Frequency The PLL characteristics are determined by ...
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Table 9. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats Standard Refresh Modes Resolution Rate (Hz) VGA 640 × 480 SVGA 800 × 600 XGA 1024 × ...
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AD9985 disappear. In other systems, such as those that employ Composite Sync (Csync) signals or embedded Sync-on-Green (SOG), Hsync includes equalization pulses or other distortions during Vsync. To avoid upsetting the clock generator during Vsync important to ignore ...
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Write and Hex Read or Default Address Read Only Bits Value 03H R/W 7:3 01****** **001*** 04H R/W 7:3 10000*** 05H 7:0 10000000 R/W 06H R/W 7:0 10000000 07H R/W 7:0 00100000 08H R/W 7:0 10000000 09H R/W 7:0 10000000 ...
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AD9985 Write and Hex Read or Default Address Read Only Bits Value *****0** ******0* *******0 11H R/W 7:0 00100000 12H R/W 7:0 00000000 13H R/W 7:0 00000000 14H RO 7:0 15H R/W 7:2 111111** 1 ******1* 0 *******1 16H R/W ...
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SERIAL CONTROL REGISTER DETAIL CHIP IDENTIFICATION 00 7–0 Chip Revision An 8-bit register that represents the silicon revision. PLL DIVIDER CONTROL 01 7–0 PLL Divide Ratio MSBs The 8 most significant bits of the 12-bit PLL divide ratio PLLDIV. ...
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AD9985 CLAMP TIMING 05 7–0 Clamp Placement An 8-bit register that sets the position of the internally generated clamp. When Clamp Function (Register 0FH, Bit clamp signal is generated internally position established by the ...
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MODE CONTROL Hsync Input Polarity Override This register is used to override the internal circuitry that determines the polarity of the Hsync signal going into the PLL. Table 13. Hsync Input Polarity Override Settings Override Bit Function ...
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AD9985 0F 7 Clamp Input Signal Source This bit determines the source of clamp timing. Table 21. Clamp Input Signal Source Settings Clamp Function Function 0 Internally Generated Clamp Signal 1 Externally Provided Clamp Signal A 0 enables the clamp ...
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Red Clamp Select This bit determines whether the Red channel is clamped to ground or to midscale. For RGB video, all three channels are referenced to ground. For YCbCr (or YUV), the Y channel is referenced to ground, ...
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AD9985 Table 33. Detected Hsync Input Polarity Status Hsync Polarity Result Status 0 Negative 1 Positive 14 4 Vsync Detect This bit is used to indicate when activity is detected on the Vsync input pin (Pin 31). If Vsync is ...
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Blue Target Code This specifies the targeted value of the final offset for the Blue channel when auto offset is employed (Register 0x1D Bit 7 = 1). Default Auto Offset Enable Enables the auto ...
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AD9985 2-WIRE SERIAL CONTROL PORT 2 A 2-wire serial control interface ( provided two AD9985 devices may be connected to the 2-wire serial interface, with each device having a unique address. The 2-wire serial interface comprises ...
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Data is read from the control registers of the AD9985 in a similar manner. Reading requires two data transfer operations: The base address must be written with the R/W bit of the slave address byte low to set up a ...
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AD9985 SYNC STRIPPER NEGATIVE PEAK SOG HSYNC IN ACTIVITY DETECT COAST VSYNC IN ACTIVITY DETECT Table 43. Control of the Sync Block Muxes via the Serial Register Serial Bus Mux No. Control Bit 1 and 2 0EH: Bit 3 3 ...
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PCB LAYOUT RECOMMENDATIONS The AD9985 is a high precision, high speed analog device. As such, to get the maximum performance from the part important to have a well laid out board. The following is a guide for designing ...
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AD9985 PLL Place the PLL loop filter components as close to the FILT pin as possible. Do not place any digital or other high frequency traces near these components. Use the values suggested in the data sheet with 10% tolerances ...
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OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE VIEW A ROTATED 90° CCW ORDERING GUIDE Model 1 AD9985KSTZ-110 1 AD9985KSTZ-140 1 AD9985BSTZ-110 AD9985/PCB Pb-free part. 0.75 1.60 0.60 MAX 0. SEATING PLANE 10° 6° ...
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AD9985 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Patent Rights to use these components © ...