ADM1060ARU Analog Devices Inc, ADM1060ARU Datasheet - Page 22

• Manufacturer Part Number: ADM1060ARU
• Description: Communications SupvSeq Circuit I.C.
• Manufacturer: Analog Devices Inc
• Type: Sequencerr

Specifications of ADM1060ARU

• Rohs Status: RoHS non-compliant
• Number Of Voltages Monitored: 7
• Output: Programmable
• Voltage - Threshold: Adjustable/Selectable
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Number Of Voltage Supervisors: 7
• Operating Supply Voltage (min): 2V
• Operating Supply Voltage (max): 14.4V
• Package Type: TSSOP
• Operating Temperature Classification: Industrial
• Operating Temp Range: -40C to 85C
• Pin Count: 28
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: EVAL-ADM1060EBZ - BOARD EVALUATION ADM1060
• Reset: -
• Reset Timeout: -
• Lead Free Status / Rohs Status: Not Compliant

ADM1060
LOGIC
PLB1
PLB3
PLB4
PLB5
PLB6
PLB7
PLB8
PLB9
PLB2
GPI1
GPI2
GPI3
GPI4
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
WDI _ P
WDI _ L
INVERT
INVERT
INVERT
INVERT
INVERT
INVERT
INVERT
INVERT
INVERT
INVERT
INVERT
INVERT
VB1
VB2
VP1
VP2
VP3
VP4
VH
0x00 P1PLBPOLA.0
0x01 P1PLBIMKA.0
0x00 P1PLBPOLA.1
0x01 P1PLBIMKA.1
0x00 P1PLBPOLA.2
0x01 P1PLBIMKA.2
0x00 P1PLBPOLA.3
0x01 P1PLBIMKA.3
0x00 P1PLBPOLA.4
0x01 P1PLBIMKA.4
0x00 P1PLBPOLA.5
0x01 P1PLBIMKA.5
0x00 P1PLBPOLA.6
0x01 P1PLBIMKA.6
0x00 P1PLBPOLA.7
0x01 P1PLBIMKA.7
0x04
0x05
0x04
0x05
0x04
0x05
0x04
0x05
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
INVERT
INVERT
INVERT
INVERT
INVERT
INVERT
INVERT
INVERT
INVERT
NOT CONNECTED
P1GPIPOL.4
P1GPIPOL.5
P1GPIPOL.6
P1GPIPOL.7
P1GPIIMK.4
P1GPIIMK.5
P1GPIIMK.6
P1GPIIMK.7
0x02 P1SFDPOLA.1
0x03 P1SFDIMKA.1
0x02 P1SFDPOLA.3
0x03 P1SFDIMKA.3
0x02 P1SFDPOLA.4
0x03 P1SFDIMKA.4
0x02 P1SFDPOLA.5
0x03 P1SFDIMKA.5
0x02 P1SFDPOLA.6
0x03 P1SFDIMKA.6
0x06
0x06
0x02 P1SFDPOLA.0
0x03 P1SFDIMKA.0
0x02 P1SFDPOLA.2
0x03 P1SFDIMKA.2
0x06
0x06
P1WDICFG.7
P1WDICFG.6
P1WDICFG.5
P1WDICFG.4
Figure 21. Detailed Diagram for Function A of PLB1
Rev. B | Page 22 of 52
0x07 P1EN.1
FUNCTION A
ENABLE
FUNCTION B
TO
0x0C P1PDBTIM.7–4
0x0C P1PDBTIM.3–0
FALL TIME
RISE TIME
PDB
0x07 P1EN.2
PLBOUT