ADP3050-BL1-EVZ Analog Devices Inc, ADP3050-BL1-EVZ Datasheet - Page 18

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ADP3050-BL1-EVZ

Manufacturer Part Number
ADP3050-BL1-EVZ
Description
Blank ADISimPower Eval ADP3050
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADP3050-BL1-EVZ

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
ADP3050
BOARD LAYOUT GUIDELINES
A good board layout is essential when designing a switching
regulator. The high switching currents along with parasitic
wiring inductances can generate significant voltage transients
and cause havoc in sensitive circuits. For best results, keep the
main switching path as tight as possible (keep L1, D1, C
C
and BOOST nodes (without violating current density require-
ments) to reduce the amount of noise coupling into other
sensitive nodes.
The external components should be located as close to the
ADP3050 as possible. For best thermal performance, use wide
copper traces for all IC connections, and always connect the
GND pin to a large piece of copper or ground plane. The additional
copper improves heat transfer from the IC, greatly reducing the
package thermal resistance. Further improvements of the thermal
performance can be made by using multilayer boards and using
vias to transfer heat to the other layers. A single layer board
layout is shown in Figure 27. The amount of copper used for the
input, output, and ground traces can be reduced, but were made
large to improve the thermal performance. For the 5 V and 3.3 V
versions, leave out R1 and R2; for the adjustable version, remove
the trace that shorts out R2. Route all sensitive traces and compo-
nents, such as those associated with feedback and compensation,
away from the BOOST and SWITCH traces.
TYPICAL APPLICATIONS
5 V to 3.3 V Buck (Stepdown) Regulator
The circuit in Figure 28 shows the ADP3050 in a buck
configuration. It is used to generate 3.3 V regulated output from
5 V input voltage with the following specifications:
V
V
I
I
V
OUT
RIPPLE
OUT
IN
OUT
OUT_RIPPLE
GND
V
= 4.5 V to 5.5 V
IN
= 0.75 A
close together) and minimize the copper area of the SWITCH
C
= 3.3 V
= 0.4 A × 0.75 A = 0.3 A
IN
= 50 mV
IN
Figure 26. Main Switching Path
ADP3050
GND
SWITCH
D1
L1
C
OUT
IN
, and
V
GND
OUT
Rev. B | Page 18 of 24
1N5817
GND
D1
V
SD
IN
5V
OUTPUT
Figure 27. Recommended Board Layout
R2
Figure 28. 5 V to 3.3 V Buck Regulator
C3
0.22µF
D2
22µH
+
L1
L1
1N4148
C1
22µF
D2
R1
C2
C1
GROUND
C2
0.01µF
1
2
3
4
ADP3050-3.3
SWITCH
BOOST
BIAS
FB
CC
D1
C3
ADP3050
U1
COMP
GND
SD
IN
INPUT
RC
8
7
6
5
7.5kΩ
R1
+ C5
C4
1nF
100µF
3.3V
V
OUT

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