ADSP-21061KSZ-133 Analog Devices Inc, ADSP-21061KSZ-133 Datasheet - Page 2
![ADSP-21061 1MBIT, 33MHz, 5v SHARC](/photos/6/71/67190/sp-240-2_sml.jpg)
ADSP-21061KSZ-133
Manufacturer Part Number
ADSP-21061KSZ-133
Description
ADSP-21061 1MBIT, 33MHz, 5v SHARC
Manufacturer
Analog Devices Inc
Series
SHARC®r
Type
Floating Pointr
Datasheet
1.ADSP-21061LKSZ-160.pdf
(56 pages)
Specifications of ADSP-21061KSZ-133
Interface
Synchronous Serial Port (SSP)
Clock Rate
33MHz
Non-volatile Memory
External
On-chip Ram
128kB
Voltage - I/o
5.00V
Voltage - Core
5.00V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
240-MQFP, 240-PQFP
Package
240MQFP
Numeric And Arithmetic Format
Floating-Point
Maximum Speed
33 MHz
Ram Size
128 KB
Device Million Instructions Per Second
33 MIPS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-21061KSZ-133
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADSP-21061/ADSP-21061L
Parallel Computations
Single-cycle multiply and ALU operations in parallel with
Multiply with add and subtract for accelerated FFT butterfly
1M bit On-Chip SRAM
Dual-ported for independent access by core processor and
Off-Chip Memory Interfacing
4 gigawords addressable
Programmable wait state generation, page-mode DRAM
DMA Controller
6 DMA channels for transfers between ADSP-21061 internal
Background DMA transfers at up to 40 MHz, in parallel with
Host Processor Interface to 16- and 32-Bit
Microprocessors
Host can directly read/write ADSP-21061 internal memory
Multiprocessing
Glueless connection for scalable DSP multiprocessing
Distributed on-chip bus arbitration for parallel bus connect
240 MBps transfer rate over parallel bus
Serial Ports
Two 40 Mbps synchronous serial ports with companding
Independent transmit and receive functions
dual memory read/write and instruction fetch
computation
DMA
support
memory and external memory, external peripherals, host
processor, or serial ports
full-speed processor execution
architecture
of up to six ADSP-21061s plus host
hardware
Rev. C | Page 2 of 56 | July 2007