ADV611JSTZ Analog Devices Inc, ADV611JSTZ Datasheet - Page 22

• Manufacturer Part Number: ADV611JSTZ
• Description: CCTV Digital Video Codec
• Manufacturer: Analog Devices Inc
• Type: Video Codecr

Specifications of ADV611JSTZ

• Data Interface: Serial
• Resolution (bits): 8 b
• Sigma Delta: No
• Voltage - Supply, Digital: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 120-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADV611/ADV612
Name
CCIR-656
Multiplex Philips
Clocks and Strobes
All video data is synchronous to the video clock (VCLK).
The rising edge of VCLK is used to clock all data into the
ADV611/ADV612.
Synchronization and Blanking Pins
Three signals, which can be configured as inputs or outputs, are
used for video frame and field horizontal synchronization and
blanking. These signals are VSYNC, HSYNC, and FIELD.
VDATA Pins Functions With Differing Video Interface Formats
The functionality of the Video Interface pins depends on the
current video format.
Video Formats—CCIR-656
The ADV611/ADV612 supports a glueless video interface to
CCIR-656 devices when the Video Format is programmed to
CCIR-656 mode. CCIR-656 requires that 4:2:2 data (8 bits per
component) be multiplexed and transmitted over a single 8-bit
physical interface. A 27 MHz clock is transmitted along with the
data. This clock is synchronous with the data. The color space of
CCIR-656 is YCrCb.
When in master mode, the CCIR-656 mode does not require
any external synchronization or blanking signals to accompany
digital video. Instead, CCIR-656 includes special time codes
in the stream syntax that define horizontal blanking periods,
HSYNC, VSYNC and FIELD
Functionality for CCIR-656
Encode Mode (video data is input
to the chip)
Decode Mode (video data is output
from the chip)
Table IX. CCIR-656 Master and Slave Modes HSYNC, VSYNC, and FIELD Functionality
Bit/
Component
8
8
Master Mode (HSYNC, VSYNC
and FIELD Are Outputs)
Pins are driven to reflect the states of the
received time codes: EAV and SAV. This
functionality is independent of the state of
the 525-625 mode control. An encoder is
most likely to be in master mode.
Pins are output to the precise timing definitions
for CCIR-656 interfaces. The state of the pins
reflect the state of the EAV and SAV timing
codes that are generated in the output video data.
These definitions are different for 525 and 625 line
systems. The ADV611/ADV612 completely manages
the generation and timing of these pins.
Color
Space
YCrCb
YUV
Table VIII. Component Digital Video Formats
Sampling
4:2:2
4:2:2
–22–
vertical blanking periods, and field synchronization (horizontal
and vertical synchronization information can be derived). These
time codes are called End-of-Active-Video (EAV) and Start-of-
Active-Video (SAV). Each line of video has one EAV and one
SAV time code. EAV and SAV have three bits of embedded
information to define HSYNC, VSYNC and Field information
as well as error detection and correction bits.
VCLK is driven with a 27 MHz, 50% duty cycle clock which is
synchronous with the video data. Video data is clocked on the
rising edge of the VCLK signal. When decoding, the VCLK
signal is typically transmitted along with video data in the
CCIR-656 physical interface.
Electrically, CCIR-656 specifies differential ECL levels to be
used for all interfaces. The ADV611/ADV612, however, only
supports unipolar, TTL logic thresholds. Systems designs that
interface to strictly conforming CCIR-656 devices (especially
when interfacing over long cable distances) must include ECL
level shifters and line drivers.
The functionality of HSYNC, VSYNC and FIELD Pins is
dependent on three programmable modes of the ADV611/
ADV612: Master-Slave Control, Encode-Decode Control and
525-625 Control. Table X summarizes the functionality of
these pins in various modes.
Nominal
Data Rate
(MHz)
27
27
Slave
Master/
Master
Either
Slave Mode (HSYNC, VSYNC
and FIELD Are Inputs)
These pins are used to control the
blanking of video and sequencing (used
with video decoders that do not con-
form to the correct number of samples
per line [e.g., the Harris 8115]).
Undefined—Use Master Mode
I/F Width
8
8
Format
Number
0x0
0x2
REV. 0