AM29F200BB-90EC Spansion Inc., AM29F200BB-90EC Datasheet - Page 10

• Manufacturer Part Number: AM29F200BB-90EC
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of AM29F200BB-90EC

• Memory Size: 2Mbit
• Memory Configuration: 256K X 8
• Ic Interface Type: Parallel
• Access Time: 90ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: 0°C To +70°C
• Termination Type: SMD
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
Legend:
L = Logic Low = V
Note: See the sections Sector Group Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at V
BYTE# pin determines whether the device outputs
array data in words or bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
8
Read
Write
CMOS Standby
TTL Standby
Output Disable
Hardware Reset
Temporary Sector Unprotect
(See Note)
Operation
IL
, H = Logic High = V
IH
. On x16 (word-wide) devices, the
V
CC
Table 1. Am29F200B Device Bus Operations
IL
CE#
. CE# is the power
± 0.5 V
IH
H
X
X
L
L
L
, V
ID
= 12.0 ± 0.5 V, X = Don’t Care, D
D A T A
OE#
H
X
X
H
X
X
L
Am29F200B
WE#
H
X
X
H
X
X
L
S H E E T
V
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device. The appropriate device bus
operations table lists the inputs and control levels
required, and the resulting output. The following sub-
sections describe each of these operations in further
detail.
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. I
table represents the active current specification for
reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
On x16 (word-wide) devices, for program operations,
the BYTE# pin determines whether the device accepts
program data in bytes or words. Refer to “Word/Byte
Configuration” for more information.
CC
RESET#
V
± 0.5 V
H
H
H
H
L
ID
IL
, and OE# to V
IN
= Data In, D
A0–A16
A
A
A
X
X
X
X
IN
IN
IN
CC1
OUT
DQ0–DQ7
IH
High-Z
High-Z
High-Z
High-Z
.
D
= Data Out, A
in the DC Characteristics
D
D
OUT
21526D4 November 1, 2006
IN
IN
BYTE#
High-Z
High-Z
High-Z
High-Z
= V
D
D
D
DQ8–DQ15
OUT
IN
IN
IN
IH
= Address In
BYTE#
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
= V
X
IL