AM29LV160DT-70EC Spansion Inc., AM29LV160DT-70EC Datasheet - Page 11

• Manufacturer Part Number: AM29LV160DT-70EC
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of AM29LV160DT-70EC

• Memory Configuration: 2M X 8 / 1M X 16
• Ic Interface Type: Parallel
• Access Time: 70ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Mounting Type: Surface Mount
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 3V
• Supply Voltage Max: 3.6V
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the system
drives the RESET# pin to V
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
IL
but not within V
SS
±0.3 V, the standby current will
IL
for at least a period of t
CC4
SS
). If RESET# is held
±0.3 V, the device
Am29LV160D
RP
,
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
system can thus monitor RY/BY# to deter mine
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is
completed within a time of t
ded Algorithms). The system can read data t
the RESET# pin returns to V
Refer to the AC Characteristics tables for RESET# pa-
rameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins are placed in the high imped-
ance state.
READY
(during Embedded Algorithms). The
IH
READY
, output from the device is
IH
.
(not during Embed-
RH
after
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