AM29LV641DH120REF Spansion Inc., AM29LV641DH120REF Datasheet - Page 31

• Manufacturer Part Number: AM29LV641DH120REF
• Description: Flash Memory IC
• Manufacturer: Spansion Inc.

Specifications of AM29LV641DH120REF

• Memory Size: 64Mbit
• Memory Configuration: 4M X 16
• Ic Interface Type: Parallel
• Access Time: 120ns
• Memory Case Style: TSOP
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +85°C
• Termination Type: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7.
describe the function of these bits. DQ7 and DQ6 each offer
a method for determining whether a program or erase oper-
ation is complete or in progress. The device also provides a
hardware-based output signal, RY/BY#, to determine
whether an Embedded Program or Erase operation is in
progress or was completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether the device is in Erase
Suspend. Data# Polling is valid after the rising edge of the
final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device out-
puts on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is ac-
tive for approximately 1 µs, at thai time the device returns to
the read mode.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status infor-
mation on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 is active for approximately 100 µs, then the
device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected. However, if the sys-
tem reads DQ7 at an address within a protected
sector, the status may not be valid.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ0–DQ6 may be still
January 22, 2007 22366C6
Table 11 on page 32
and the following subsections
Am29LV640D/Am29LV641D
D A T A
S H E E T
invalid. Valid data on DQ0–DQ7 appears on succes-
sive read cycles.
Table 11 on page 32
ing on DQ7.
Polling algorithm.
Characteristics
diagram.
Notes:
1. VA = Valid address for programming. During a sector
2. DQ7 should be rechecked even if DQ5 = “1” because
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
DQ7 may change simultaneously with DQ5.
No
Figure 5. Data# Polling Algorithm
Read DQ7–DQ0
Read DQ7–DQ0
Figure 5, on page 29
DQ7 = Data?
DQ7 = Data?
Addr = VA
Addr = VA
section shows the Data# Polling timing
DQ5 = 1?
START
FAIL
Figure 18, on page 42
No
Yes
No
shows the outputs for Data# Poll-
Yes
Yes
shows the Data#
PASS
in the
AC
29